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P4080 PCIe Adapter SDK User Guide Production Release

P4080 PCIe Adapter SDK User Guide Production Release

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Freescale Semiconductor<br />

1.1 <strong>P4080</strong> PCIE <strong>Adapter</strong> Overview<br />

Figure 1 <strong>P4080</strong> PCIE <strong>Adapter</strong> Block Diagram<br />

The <strong>P4080</strong> multi-core processor of the adapter combines eight Power Architecture e500mc cores with a<br />

Datapath Acceleration Architecture (DPAA) that includes the following acceleration blocks [1]:<br />

Frame Manger (FMAN) - Packet parsing, classification and distribution<br />

Queue Manager (QMAN) - Queue management for scheduling, packet sequencing and congestion<br />

management<br />

Buffer Manager (BMAN) - Hardware Buffer management for buffer allocation and de-allocation<br />

Cryptographic Security Acceleration (SEC 4.0)<br />

RegEx Pattern Matching (PME 2.0)<br />

The card also provides the following integrated functions:<br />

One X8 PCIE Gen1 Interface<br />

1 1G RGMII Management Port<br />

© Freescale Semiconductor, Inc., 2011. All rights reserved.<br />

Freescale Confidential Proprietary Page 3

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