P4080 PCIe Adapter SDK User Guide Production Release

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Freescale Semiconductor File system (used in RAM disk) that contains the needed user space files including USDPAA example application binaries. Linux must be booted using this file system. All six of the files listed above are needed to run USDPAA on the card. The first three must be programmed into the NOR flash. The last three may be programmed into the NOR flash, but also may be loaded into RAM by u-boot using the tftp protocol. U-boot is also capable of loading files into RAM via tftp and then programming them into the NOR flash. In all cases, you must have access to a tftp server, ideally on your Linux development host. Copy the six files listed above to a directory from which they can be accessed via your tftp server. U-boot on the P4080 PCIE Adapter must use tftp to access them. Details of installing and configuring a tftp server on your development host are specific to your host Linux distribution. 6.6 Programming P4080 PCIE Adapter NOR Flash Bank 0 The P4080 PCIE Adapter has a feature that uses address swizzling to make it appear that the NOR flash is divided into multiple parts-- this document will assume two. The parts are called “bank 0” and “bank 4”. When you power-on or reset, u-boot will boot from bank 0. U-boot in bank 0 can program images into bank 4. Then, you can enter “n710_reset altbank” from the bank 0 u-boot prompt to boot into bank 4. It is recommended to leave the bank 0 images alone and simply use them to program images into bank 4. This is to ensure that you always have working images in bank 0. Programming Bank 0 should only be used, once the images have been validated in bank 4. U-boot Boot Text Below is a reference text of u-boot bootup U-Boot MPS N710 2010.12 (Sep 20 2011 - 13:24:26) CPU0: P4080E, Version: 2.0, (0x82080020) Core: E500MC, Version: 2.0, (0x80230020) Clock Configuration: CPU0:1333.333 MHz, CPU1:1333.333 MHz, CPU2:1333.333 MHz, CPU3:1333.333 M CPU4:1333.333 MHz, CPU5:1333.333 MHz, CPU6:1333.333 MHz, CPU7:1333.333 M CCB:666.667 MHz, © Freescale Semiconductor, Inc., 2011. All rights reserved. Freescale Confidential Proprietary Page 36
Freescale Semiconductor DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:83.333 MHz FMAN1: 500 MHz FMAN2: 500 MHz PME: 333.333 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Sys ID: 0x0711, Board Version 0x 0, CPLD Ver: 0x0336-bit Addressing Reset Configuration Word (RCW): 00000000: 10600000 00000000 20201820 0000cccc 00000010: 08402200 3c3c2000 de800000 61000000 00000020: 00300000 00000000 00000000 008b0000 00000030: 00000000 00000000 00000000 00000000 I2C: ready DRAM: Initializing....using SPD Detected RDIMM(s) Detected RDIMM(s) CS2 is disabled. CS3 is disabled. CS2 is disabled. CS3 is disabled. Implementing recommended DDR3 Init sequence Enabling controller 0 Enabling controller 1 2 GiB left unmapped DDR: 4 GiB (DDR3, 64-bit, CL=9, ECC on) DDR Controller Interleaving Mode: cache line DDR Chip-Select Interleaving Mode: CS0+CS1 Testing 0x00000000 - 0x7fffffff Testing 0x80000000 - 0xffffffff Remap DDR 2 GiB left unmapped Relocating u-boot to 0x7ff30000 POST memory PASSED FLASH: 128 MiB L2: 128 KB enabled Corenet Platform Cache: 2048 KB enabled p4080_erratum_serdes8 enable Bank3 p4080_erratum_serdes8 enable Bank2 p4080_erratum_serdes9 reset Bank2 p4080_erratum_serdes9 reset Bank3 MMC: FSL_ESDHC: 0 EEPROM: N710 v2 PCIe1: Endpoint, with errors. Clearing. Now 0x00000000 Setting up PCIE Outbound Regions Region 0: bus start = 0x0 bus end = 0x20000000 phys_start = 0xc00000000 Outbound memory range: 0:20000000 PCICSRBAR @ 0xff000000 © Freescale Semiconductor, Inc., 2011. All rights reserved. Freescale Confidential Proprietary Page 37
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P4080 PCIe Adapter SDK User Guide Production Release

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