AN4365, Qorivva MPC56xx Flash Programming Through Nexus/JTAG

Qorivva MPC56xx Flash Programming Through Nexus/JTAG, Rev. 0
On-Chip Emulation (OnCE)
Figure 9 shows reading the value 0x80000000 from DBCR0 through the DR path assuming the TAP
controller state machine is initially in the RUN-TEST/IDLE state. The state machine is returned to the
RUN-TEST/IDLE state when the read is complete.
2.3 OnCE Status Register
Figure 9. Signal transitions for reading DBCR0
The OnCE Status Register (OSR) is a special register in terms of how it is read. Status information related
to the state of the CPU is latched into the OnCE Status Register when the OnCE TAP controller state
machine enters the CAPTURE-IR state. The status information is shifted out serially through the
SHIFT-IR state on TDO. The OSR is a 10-bit register like the OCMD. Therefore, the status information
can be read while writing OCMD. The OSR is shown in Figure 10.
0 1 2 3 4 5 6 7 8 9
MCLK ERR CHKSTOP RESET HALT STOP DEBUG 0 1
Figure 10. OnCE Status Register (OSR)
Figure 11 shows reading the OnCE status register on TDO while writing the OCMD on TDI assuming the
TAP controller state machine is initially in the RUN-TEST/IDLE state. The state machine is returned to
the RUN-TEST/IDLE state when the read is complete. The OCMD is written with the value
0b10_0001_0001 choosing a read of No Register Selected. The data read on TDO from the OnCE status
register is 0b10_0000_1001 showing that the OSR[MCLK] and OSR[DEBUG] status bits are set. All data
is scanned in and out least significant bit first.
Freescale Semiconductor 13