AN4365, Qorivva MPC56xx Flash Programming Through Nexus/JTAG

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Figure 1. TAP controller finite state machine Qorivva MPC56xx Flash Programming Through Nexus/JTAG, Rev. 0 JTAG Freescale Semiconductor 4
1.3 JTAG Controller (JTAGC) The devices in the MPC56xx family have a JTAG controller (JTAGC) that enables both boundary scan and communication with the Nexus Development Interface (NDI). A block diagram of the NDI is shown in Figure 2. NDEDI R/W Register, Halt, Step, Continue JCOMP Engine 1 eTPU CDC Engine 2* Program, Data, Ownership, Watchpoint, Trace Buffer 1.3.1 JTAGC reset NZ6C3 e200z6 R/W Register, R/W Data, Halt, Step, Continue JTAG Port Controller (JTAGC) Program, Data, Ownership, Watchpoint, Trace Nexus Port Controller (NPC) RDY TDI TCK TDO TMS EVTI Cache Read/Write Access eDMAC XBAR Data, Watchpoint, Trace Figure 2. Nexus Development Interface (NDI) functional block diagram Qorivva MPC56xx Flash Programming Through Nexus/JTAG, Rev. 0 JTAG The JTAGC is placed in reset when the TAP controller state machine is in the test logic reset state. The test logic reset state is entered upon the assertion of the power-on reset signal, negation of JCOMP, or through TAP controller state machine transitions controlled by TMS. Asserting power-on reset or negating JCOMP results in asynchronous entry into the test logic reset state. In devices without a JCOMP pin, the JTAGC is always enabled and can only be reset by clocking TCK five times with TMS high. See AN4088, “MPC5500/MPC5600 Nexus Support Overview” for a table of devices that implement the JCOMP pin. Freescale Semiconductor 5 MMU Buffer NXDM Buffer Auxiliary Port • • • Off-Chip Memory & I/O On-Chip Memory & I/O FlexRay NXFR Data, Watchpoint, Trace Buffer MSEO[0:1] MCKO MDO(4 or 12) EVTO * Some MPC55xx devices have one eTPU engine, others have two engines.
Page 1 and 2: Freescale Semiconductor Application
Page 3: 1.2 TAP controller state machine Th
Page 7 and 8: Qorivva MPC56xx Flash Programming T
Page 9 and 10: Table 4. OCMD bit definitions (cont
Page 23 and 24: Table 7 details the status bit enco
Page 25 and 26: Nexus register index Value shown at
Page 35 and 36: Appendix A Demo calling basic SSD f
Page 37 and 38: symbol BUFFER_SIZE $800 symbol STAC
Page 39 and 40: ; Set PC PC Addr_GetLock ; Run go Q
Page 41 and 42: PC Addr_SetLock ; Run go Qorivva MP
Page 43 and 44: ; Pass input arguments R3 pSSDConfi

AN4365, Qorivva MPC56xx Flash Programming Through Nexus/JTAG

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