AN4365, Qorivva MPC56xx Flash Programming Through Nexus/JTAG

2.6.1 Instruction Register (IR)
Figure 14. CPU Status and Control Scan Chain Register
Qorivva MPC56xx Flash Programming Through Nexus/JTAG, Rev. 0
On-Chip Emulation (OnCE)
After entering debug mode, the opcode of the next instruction to be executed will be in the Instruction
Register (IR). The value in the IR should be saved for later restoration if continuation of the normal
instruction stream is desired.
The external tool has the capability to put instructions directly into the IR via the CPUSCR. These
instructions can then be executed by the debug control block. By selecting appropriate instructions and
single stepping them, the external tool can examine or change memory locations or CPU registers. See
Section 2.7, “Single step,” for details on single step.
2.6.2 Control State register (CTL)
0
32
WBBR low
31
0
32
WBBR high
31
32
0 31
MSR
32
0 31
PC
32
0 31
IR
32
0 31
CTL
The Control State register (CTL) stores the value of certain internal CPU state variables before debug
mode is entered. Figure 15 shows the CTL register. Some MPC56xx devices have additional bit fields
populated in the bit range 0–15. These bits are not important in the context of this document. For further
information, please see the relevant e200zx core guide, available at www.freescale.com.
Freescale Semiconductor 16
TDO
TCK
TDI