AN4365, Qorivva MPC56xx Flash Programming Through Nexus/JTAG

• Nexus3 burst read, see Section 3.5, “Burst block memory read access.”
• MMU initialization, see Section 4.1, “Setting up the memory management unit.”
• Internal SRAM initialization, see Section 4.2, “Internal SRAM initialization.”
• FMPLL initialization, see Section 4.3, “FMPLL initialization.”
• S-record parser and loader.
• Debug and driver initialization, see Section 5.2.1, “Debug and driver initialization.”
• Flash initialization, see Section 5.2.2, “FlashInit.”
• Flash block lock initialization, see Section 5.2.3, “SetLock.”
• Flash erase, see Section 5.2.4, “FlashErase.”
• Flash program, see Section 5.2.5, “FlashProgram.”
6 References
For further information, please refer to the documents listed in Table 10.
7 Revision history
Table 10. References
Document Title Availability
Qorivva MPC56xx Flash Programming Through Nexus/JTAG, Rev. 0
References
AN2865 MPC5500 & MPC5600 Simple Cookbook www.freescale.com
AN3283 MPC5500 Flash Programming Through Nexus/JTAG
AN3968 Nexus Interface Connector for the MPC567xF and MPC5676R Families
AN4088 MPC5500/MPC5600 Nexus Support Overview
e200z0CORERM e200z0 Power Architecture ® Core Reference Manual
e200z1RM e200z1 Power Architecture Core Reference Manual
e200z3CORERM e200z1 Power Architecture Core Reference Manual
e200z4RM e200z4 Power Architecture Core Reference Manual
e200z6RM e200z6 PowerPC Core Reference Manual
e200z760RM e200z760 Power Architecture Core Reference Manual
Table 11. Changes made April 2012 1
Section Description
Front page Add SafeAssure branding.
Title and text on first page Add Qorivva branding.
Back page Apply new back page format.
1
No substantive changes were made to the content of this document; therefore the revision number was not
incremented.
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