HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

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DDR Registered DIMMs � Address signals - Registered — Data/Strobe — Address/Control HyperLynx – High Speed PCB Design Workshop 10
DDR Electrical Characteristics — DDR uses SSTL_2 buffer technology � 2.5V technology � Class I drivers for point to point connection – Half drive strength � Class II drivers for multi-drop connection – Full drive strength — Some important voltages to remember � Vref = 1.25V — Used for setting up timing thresholds (Vih and Vil) — Must be kept stable � Vih = 1.56V Nominal — Vref + 0.31 - Logic high threshold � Vil = 0.97V Nominal — Vref – 0.31 - Logic low threshold Vih Vref Vil HyperLynx – High Speed PCB Design Workshop 11
Page 1 and 2: Mentor Graphics DDR DDR Memory So S
Page 3 and 4: *Courtesy of Hynix Semiconductor Me
Page 5 and 6: � DDR Operating Speeds — DDR200
Page 7 and 8: � Termination — Requires series
Page 9: DDR Unbuffered DIMMs � Address si
Page 13 and 14: DDR Impedance Characteristics — R
Page 15 and 16: DDR2 Bandwidth � Not necessarily
Page 17 and 18: DDR2 On Die Termination � How ODT
Page 19 and 20: — Data/Strobe DDR2 Unbuffered DIM
Page 21 and 22: DDR2 Electrical Characteristics —
Page 23 and 24: DDR2 Timing Characteristics � Sig
Page 25 and 26: DDR2 Timing Characteristics � Set
Page 27 and 28: � Why Derating? DDR2 Timing Chara
Page 29 and 30: Agenda DDR Memory design 1. DDR/DDR
Page 31 and 32: DDR/DDR2 Design Challenges Address
Page 33 and 34: DDR/DDR2 Design Challenges Power Pl
Page 35 and 36: DDR Design Guidelines � What resu
Page 37 and 38: DDR Design Guidelines � What resu
Page 39 and 40: DDR Design Guidelines � Spacing R
Page 41 and 42: DDR2 Design Guidelines � What res
Page 43 and 44: DDR2 Design Guidelines � What res
Page 45 and 46: DDR2 Design Guidelines � Spacing
Page 47 and 48: Data Rate System support Signaling
Page 49 and 50: DDR3 Market Trends � Main growth
Page 51 and 52: Lower Power � Supply voltage redu
Page 53 and 54: Fly-by Architecture � Address, Co
Page 55 and 56: Termination � On-Die Termination
Page 57 and 58: Agenda DDR Memory design 1. DDR/DDR
Page 59 and 60: Additional Technology Design kits
Page 61 and 62:
Acknowledgments � Special thanks
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