HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

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DDR2 Design Guidelines � What results are important — #4 This constraint is very critical. — A data group (DQ) has an associated strobe (DQS); — This group should be length matched to each other with minimum skew — Typical constraints are about 50 mils within the group � Try to spread this out across the channel � +/- 30 mils for length #1 � +/- 20 mils for length #2 � Overall skew between byte lanes should be +/- 500 mils � Skew between address nets should be +/- 200 mils Memory Controller HyperLynx – High Speed PCB Design Workshop DIMM Slot 1 VDD DIMM Slot 2 44 VTT VTT Pull-up Resistors
DDR2 Design Guidelines � Spacing Recommendations — Varies depending on stackup — Typically rules of thumb say 3H spacing � For a 5 mil dielectric this would be 15 mils � For signals coupled closely to reference planes, often 1.5H can be used or ~8 mils HyperLynx – High Speed PCB Design Workshop 45
Page 1 and 2: Mentor Graphics DDR DDR Memory So S
Page 3 and 4: *Courtesy of Hynix Semiconductor Me
Page 5 and 6: � DDR Operating Speeds — DDR200
Page 7 and 8: � Termination — Requires series
Page 9 and 10: DDR Unbuffered DIMMs � Address si
Page 11 and 12: DDR Electrical Characteristics —
Page 13 and 14: DDR Impedance Characteristics — R
Page 15 and 16: DDR2 Bandwidth � Not necessarily
Page 17 and 18: DDR2 On Die Termination � How ODT
Page 19 and 20: — Data/Strobe DDR2 Unbuffered DIM
Page 21 and 22: DDR2 Electrical Characteristics —
Page 23 and 24: DDR2 Timing Characteristics � Sig
Page 25 and 26: DDR2 Timing Characteristics � Set
Page 27 and 28: � Why Derating? DDR2 Timing Chara
Page 29 and 30: Agenda DDR Memory design 1. DDR/DDR
Page 31 and 32: DDR/DDR2 Design Challenges Address
Page 33 and 34: DDR/DDR2 Design Challenges Power Pl
Page 35 and 36: DDR Design Guidelines � What resu
Page 37 and 38: DDR Design Guidelines � What resu
Page 39 and 40: DDR Design Guidelines � Spacing R
Page 41 and 42: DDR2 Design Guidelines � What res
Page 43: DDR2 Design Guidelines � What res
Page 47 and 48: Data Rate System support Signaling
Page 49 and 50: DDR3 Market Trends � Main growth
Page 51 and 52: Lower Power � Supply voltage redu
Page 53 and 54: Fly-by Architecture � Address, Co
Page 55 and 56: Termination � On-Die Termination
Page 57 and 58: Agenda DDR Memory design 1. DDR/DDR
Page 59 and 60: Additional Technology Design kits
Page 61 and 62: Acknowledgments � Special thanks

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