HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

More documents

Recommendations

Info

Agenda DDR Memory design 1. DDR/DDR2 Technology Overview 2. DDR/DDR2 Challenges and Layout Guidelines 3. Introduction to DDR3 4. Wrap up Strobe HyperLynx – High Speed PCB Design Workshop 46 Data
Data Rate System support Signaling Technology DQS signals ODT Signal leveling DDR Feature Comparison DDR 200 - 400 Mbps 4 slots – 8 loads SSTL_2 Bi-directional single ended No No DDR2 400 – 800 Mbps 2 slots – 4 loads SSTL_18 Bi-directional single or differential Yes No DDR3 SSTL_15 Bi-directional differential Yes Yes HyperLynx – High Speed PCB Design Workshop 800 – 1600 Mbps 2 slots – 4 loads 1600 Mbps = 1 slot 47
Page 1 and 2: Mentor Graphics DDR DDR Memory So S
Page 3 and 4: *Courtesy of Hynix Semiconductor Me
Page 5 and 6: � DDR Operating Speeds — DDR200
Page 7 and 8: � Termination — Requires series
Page 9 and 10: DDR Unbuffered DIMMs � Address si
Page 11 and 12: DDR Electrical Characteristics —
Page 13 and 14: DDR Impedance Characteristics — R
Page 15 and 16: DDR2 Bandwidth � Not necessarily
Page 17 and 18: DDR2 On Die Termination � How ODT
Page 19 and 20: — Data/Strobe DDR2 Unbuffered DIM
Page 21 and 22: DDR2 Electrical Characteristics —
Page 23 and 24: DDR2 Timing Characteristics � Sig
Page 25 and 26: DDR2 Timing Characteristics � Set
Page 27 and 28: � Why Derating? DDR2 Timing Chara
Page 29 and 30: Agenda DDR Memory design 1. DDR/DDR
Page 31 and 32: DDR/DDR2 Design Challenges Address
Page 33 and 34: DDR/DDR2 Design Challenges Power Pl
Page 35 and 36: DDR Design Guidelines � What resu
Page 37 and 38: DDR Design Guidelines � What resu
Page 39 and 40: DDR Design Guidelines � Spacing R
Page 41 and 42: DDR2 Design Guidelines � What res
Page 43 and 44: DDR2 Design Guidelines � What res
Page 45: DDR2 Design Guidelines � Spacing
Page 49 and 50: DDR3 Market Trends � Main growth
Page 51 and 52: Lower Power � Supply voltage redu
Page 53 and 54: Fly-by Architecture � Address, Co
Page 55 and 56: Termination � On-Die Termination
Page 57 and 58: Agenda DDR Memory design 1. DDR/DDR
Page 59 and 60: Additional Technology Design kits
Page 61 and 62: Acknowledgments � Special thanks

HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

Create successful ePaper yourself

Delete template?

Save as template?