HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

More documents

Recommendations

Info

DDR Overview � Double Data Rate (DDR) Memory — Data is “clocked” in on both the rising and falling edge of the synchronous strobe signal � Source-synchronous interface — Clock (Strobe) is routed along the same path as the data — Data/Strobe signals are bi-directional — Each data group has a corresponding strobe to minimize skew (data groups are 4, 8, or 16 bits wide) and optimize timing DQS DQ0 DQ1 DQ2 Strobe HyperLynx – High Speed PCB Design Workshop 4 DQS DQ0 DQ1 DQ2 Data
� DDR Operating Speeds — DDR200 (100 MHz clock) — DDR266 (133 MHz clock) — DDR333 (166.67 MHz clock) — DDR400 (200 MHz clock) DDR Technology Memory Controller Strobe Series Resistor HyperLynx – High Speed PCB Design Workshop DIMM Slot 1 DIMM Slot 2 Data Data 5 VTT Pull-up Resistors
Page 1 and 2: Mentor Graphics DDR DDR Memory So S
Page 3: *Courtesy of Hynix Semiconductor Me
Page 7 and 8: � Termination — Requires series
Page 9 and 10: DDR Unbuffered DIMMs � Address si
Page 11 and 12: DDR Electrical Characteristics —
Page 13 and 14: DDR Impedance Characteristics — R
Page 15 and 16: DDR2 Bandwidth � Not necessarily
Page 17 and 18: DDR2 On Die Termination � How ODT
Page 19 and 20: — Data/Strobe DDR2 Unbuffered DIM
Page 21 and 22: DDR2 Electrical Characteristics —
Page 23 and 24: DDR2 Timing Characteristics � Sig
Page 25 and 26: DDR2 Timing Characteristics � Set
Page 27 and 28: � Why Derating? DDR2 Timing Chara
Page 29 and 30: Agenda DDR Memory design 1. DDR/DDR
Page 31 and 32: DDR/DDR2 Design Challenges Address
Page 33 and 34: DDR/DDR2 Design Challenges Power Pl
Page 35 and 36: DDR Design Guidelines � What resu
Page 37 and 38: DDR Design Guidelines � What resu
Page 39 and 40: DDR Design Guidelines � Spacing R
Page 41 and 42: DDR2 Design Guidelines � What res
Page 43 and 44: DDR2 Design Guidelines � What res
Page 45 and 46: DDR2 Design Guidelines � Spacing
Page 47 and 48: Data Rate System support Signaling
Page 49 and 50: DDR3 Market Trends � Main growth
Page 51 and 52: Lower Power � Supply voltage redu
Page 53 and 54: Fly-by Architecture � Address, Co
Page 55 and 56:
Termination � On-Die Termination
Page 57 and 58:
Agenda DDR Memory design 1. DDR/DDR
Page 59 and 60:
Additional Technology Design kits
Page 61 and 62:
Acknowledgments � Special thanks
show all

HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

Create successful ePaper yourself

Delete template?

Save as template?