HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

More documents

Recommendations

Info

DDR Design Guidelines � What results are important — We need to constrain 4 critical lengths 1. Net length from the controller to the 1st DIMM slot 2. Net length between DIMM slots 3. Net length from last slot to the Termination 4. All DQS/DQ groups Memory should be length Controller matched to minimize skew within the group and across the channel VDD VTT #1 #2 #3 HyperLynx – High Speed PCB Design Workshop DIMM Slot 1 DIMM Slot 2 VTT Pull-up Resistors 34
DDR Design Guidelines � What results are important — #1 This length is typically between 2” and 6” but dependant on the controller used and how many DIMMs are supported in a channel — Keep the series terminator as close as possible to the controller - typically within 1” � This length counts as part of the overall constraint for length #1 Memory Controller HyperLynx – High Speed PCB Design Workshop VDD #1 35 DIMM Slot 1
Page 1 and 2: Mentor Graphics DDR DDR Memory So S
Page 3 and 4: *Courtesy of Hynix Semiconductor Me
Page 5 and 6: � DDR Operating Speeds — DDR200
Page 7 and 8: � Termination — Requires series
Page 9 and 10: DDR Unbuffered DIMMs � Address si
Page 11 and 12: DDR Electrical Characteristics —
Page 13 and 14: DDR Impedance Characteristics — R
Page 15 and 16: DDR2 Bandwidth � Not necessarily
Page 17 and 18: DDR2 On Die Termination � How ODT
Page 19 and 20: — Data/Strobe DDR2 Unbuffered DIM
Page 21 and 22: DDR2 Electrical Characteristics —
Page 23 and 24: DDR2 Timing Characteristics � Sig
Page 25 and 26: DDR2 Timing Characteristics � Set
Page 27 and 28: � Why Derating? DDR2 Timing Chara
Page 29 and 30: Agenda DDR Memory design 1. DDR/DDR
Page 31 and 32: DDR/DDR2 Design Challenges Address
Page 33: DDR/DDR2 Design Challenges Power Pl
Page 37 and 38: DDR Design Guidelines � What resu
Page 39 and 40: DDR Design Guidelines � Spacing R
Page 41 and 42: DDR2 Design Guidelines � What res
Page 43 and 44: DDR2 Design Guidelines � What res
Page 45 and 46: DDR2 Design Guidelines � Spacing
Page 47 and 48: Data Rate System support Signaling
Page 49 and 50: DDR3 Market Trends � Main growth
Page 51 and 52: Lower Power � Supply voltage redu
Page 53 and 54: Fly-by Architecture � Address, Co
Page 55 and 56: Termination � On-Die Termination
Page 57 and 58: Agenda DDR Memory design 1. DDR/DDR
Page 59 and 60: Additional Technology Design kits
Page 61 and 62: Acknowledgments � Special thanks

HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?