HyperLynx – High Speed PCB Design Workshop - RTP Designers ...
HyperLynx – High Speed PCB Design Workshop - RTP Designers ...
HyperLynx – High Speed PCB Design Workshop - RTP Designers ...
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
DDR2 <strong>Design</strong> Guidelines<br />
� What results are important<br />
— We need to constrain 4 critical lengths<br />
1. Net length from the controller to the 1st DIMM slot<br />
2. Net length between DIMM slots<br />
3. Net length from last<br />
slot to the pull-up termination<br />
(only Address/Command)<br />
Memory<br />
4. All DQS/DQ groups<br />
Controller<br />
should be length<br />
matched to minimize<br />
skew within the group<br />
and across the channel<br />
<strong>HyperLynx</strong> <strong>–</strong> <strong>High</strong> <strong>Speed</strong> <strong>PCB</strong> <strong>Design</strong> <strong>Workshop</strong><br />
VDD VTT<br />
#1 #2 #3<br />
DIMM Slot 1<br />
DIMM Slot 2<br />
41<br />
VTT Pull-up Resistors