HyperLynx – High Speed PCB Design Workshop - RTP Designers ...

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DDR2 Timing Characteristics — Flight time measurements into a JEDEC test load � 25 ohm pull-up to Vtt (nominally 900 mV) — Some important timing parameters needed for timing equations � Setup time parameters — Tck = Clock cycle time — Tipw = DQ and DM pulse width — Tdipw = Address Control pulse width — Tdqsh/l = DQS high/low pulse width — Tds = DQ and DM setup time to DQS — Tdqsq = DQS setup skew from associated DQ/DM signals — Tdss = Falling edge DQS to CLK setup time — Tis = Address/CMD setup time to CLK � Hold time parameters — Tck = Clock cycle time — Tipw = DQ and DM pulse width — Tdipw = Address Control pulse width — Tdqsh/l = DQS high/low pulse width — Tdh = DQ and DM hold time to DQS — Tdqhq = DQS hold skew between associated DQ/DM signals — Tdsh = Falling edge DQS hold time from CLK — Tih = Address/CMD hold time to CLK HyperLynx – High Speed PCB Design Workshop 22
DDR2 Timing Characteristics � Signal derating required to meet setup and hold times — Find nominal slew rate � Setup � Hold HyperLynx – High Speed PCB Design Workshop 23
Page 1 and 2: Mentor Graphics DDR DDR Memory So S
Page 3 and 4: *Courtesy of Hynix Semiconductor Me
Page 5 and 6: � DDR Operating Speeds — DDR200
Page 7 and 8: � Termination — Requires series
Page 9 and 10: DDR Unbuffered DIMMs � Address si
Page 11 and 12: DDR Electrical Characteristics —
Page 13 and 14: DDR Impedance Characteristics — R
Page 15 and 16: DDR2 Bandwidth � Not necessarily
Page 17 and 18: DDR2 On Die Termination � How ODT
Page 19 and 20: — Data/Strobe DDR2 Unbuffered DIM
Page 21: DDR2 Electrical Characteristics —
Page 25 and 26: DDR2 Timing Characteristics � Set
Page 27 and 28: � Why Derating? DDR2 Timing Chara
Page 29 and 30: Agenda DDR Memory design 1. DDR/DDR
Page 31 and 32: DDR/DDR2 Design Challenges Address
Page 33 and 34: DDR/DDR2 Design Challenges Power Pl
Page 35 and 36: DDR Design Guidelines � What resu
Page 37 and 38: DDR Design Guidelines � What resu
Page 39 and 40: DDR Design Guidelines � Spacing R
Page 41 and 42: DDR2 Design Guidelines � What res
Page 43 and 44: DDR2 Design Guidelines � What res
Page 45 and 46: DDR2 Design Guidelines � Spacing
Page 47 and 48: Data Rate System support Signaling
Page 49 and 50: DDR3 Market Trends � Main growth
Page 51 and 52: Lower Power � Supply voltage redu
Page 53 and 54: Fly-by Architecture � Address, Co
Page 55 and 56: Termination � On-Die Termination
Page 57 and 58: Agenda DDR Memory design 1. DDR/DDR
Page 59 and 60: Additional Technology Design kits
Page 61 and 62: Acknowledgments � Special thanks

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