Implementing Audio IP in SDI II on Arria V Development Board - Altera
Implementing Audio IP in SDI II on Arria V Development Board - Altera
Implementing Audio IP in SDI II on Arria V Development Board - Altera
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10<br />
Test<str<strong>on</strong>g>in</str<strong>on</strong>g>g <str<strong>on</strong>g>Audio</str<strong>on</strong>g> Loopback<br />
AN-697<br />
2013-12-20<br />
b. On the Tools menu, click Programmer to download \\a5_sdi_audio_top.sof to the board.<br />
The software automatically detects the file dur<str<strong>on</strong>g>in</str<strong>on</strong>g>g compilati<strong>on</strong> and it appears <strong>on</strong> the pop-up w<str<strong>on</strong>g>in</str<strong>on</strong>g>dow.<br />
c. Select Device 2 <str<strong>on</strong>g>in</str<strong>on</strong>g> the FPGA development board to be the target of the programm<str<strong>on</strong>g>in</str<strong>on</strong>g>g.<br />
d. Click Start to download the file to the board. If the file does not appear <str<strong>on</strong>g>in</str<strong>on</strong>g> the pop-up w<str<strong>on</strong>g>in</str<strong>on</strong>g>dows, click<br />
Add File, navigate to \\a5_sdi_audio_top.sof and click Open.<br />
e. Reload each time after you power up the board because this design is volatile.<br />
When you have successfully set up the board, you can run the different variants discussed <str<strong>on</strong>g>in</str<strong>on</strong>g> the follow<str<strong>on</strong>g>in</str<strong>on</strong>g>g<br />
secti<strong>on</strong>s.<br />
Test<str<strong>on</strong>g>in</str<strong>on</strong>g>g <str<strong>on</strong>g>Audio</str<strong>on</strong>g> Loopback<br />
Only the <str<strong>on</strong>g>SDI</str<strong>on</strong>g> duplex <str<strong>on</strong>g>in</str<strong>on</strong>g>stance loops back the audio <str<strong>on</strong>g>in</str<strong>on</strong>g>to the transmitter. The <str<strong>on</strong>g>SDI</str<strong>on</strong>g> duplex <str<strong>on</strong>g>in</str<strong>on</strong>g>stance is able to<br />
loop back because it has both the video pattern generator and the transmitter <str<strong>on</strong>g>in</str<strong>on</strong>g> the same clock doma<str<strong>on</strong>g>in</str<strong>on</strong>g>. If<br />
you want to perform a parallel loopback for the data received from another clock doma<str<strong>on</strong>g>in</str<strong>on</strong>g> to this transmitter,<br />
you need a voltage c<strong>on</strong>trolled crystal oscillator (VCXO) to synchr<strong>on</strong>ize the data between the two clock<br />
doma<str<strong>on</strong>g>in</str<strong>on</strong>g>s. To test the audio loopback, do the follow<str<strong>on</strong>g>in</str<strong>on</strong>g>g steps.<br />
1. C<strong>on</strong>nect an <str<strong>on</strong>g>SDI</str<strong>on</strong>g> signal generator with an embedded audio or <str<strong>on</strong>g>SDI</str<strong>on</strong>g> OUT 2 to the receiver <str<strong>on</strong>g>SDI</str<strong>on</strong>g> IN1.<br />
2. C<strong>on</strong>nect an <str<strong>on</strong>g>SDI</str<strong>on</strong>g> signal analyzer with the embedded audio enabled to the transmitter <str<strong>on</strong>g>SDI</str<strong>on</strong>g> OUT1.<br />
3. C<strong>on</strong>nect the AES OUT 1 to AES IN 1 us<str<strong>on</strong>g>in</str<strong>on</strong>g>g the BNC cable for the audio data external loopback.<br />
4. Switch between the different video standards (SD, HD, 3GA or 3GB) by c<strong>on</strong>troll<str<strong>on</strong>g>in</str<strong>on</strong>g>g user2 D<str<strong>on</strong>g>IP</str<strong>on</strong>g> switch,<br />
as <str<strong>on</strong>g>in</str<strong>on</strong>g>dicated <str<strong>on</strong>g>in</str<strong>on</strong>g> Table 2.<br />
5. Check the video pattern result <str<strong>on</strong>g>in</str<strong>on</strong>g> the <str<strong>on</strong>g>SDI</str<strong>on</strong>g> signal analyzer.<br />
6. When you enable the embedded audio <str<strong>on</strong>g>in</str<strong>on</strong>g>put <str<strong>on</strong>g>in</str<strong>on</strong>g> the <str<strong>on</strong>g>SDI</str<strong>on</strong>g> signal analyzer, you can observe the audio<br />
embedded <str<strong>on</strong>g>in</str<strong>on</strong>g> the follow<str<strong>on</strong>g>in</str<strong>on</strong>g>g groups:<br />
a. SD standard: Group 1<br />
b. HD standard: Groups 1 and 2<br />
c. 3GA standard: Groups 1, 2, and 3<br />
d. 3GB standard: Groups 1, 2, 3, and 4<br />
7. Check the audio pattern result us<str<strong>on</strong>g>in</str<strong>on</strong>g>g the embedded audio <str<strong>on</strong>g>SDI</str<strong>on</strong>g> signal analyzer.<br />
8. You can select the audio data to be embedded <str<strong>on</strong>g>in</str<strong>on</strong>g> <str<strong>on</strong>g>SDI</str<strong>on</strong>g> OUT1 from the <str<strong>on</strong>g>in</str<strong>on</strong>g>ternal loopback through the<br />
Clocked <str<strong>on</strong>g>Audio</str<strong>on</strong>g> Input and Clocked <str<strong>on</strong>g>Audio</str<strong>on</strong>g> Output paths, the external loopback without the sample rate<br />
c<strong>on</strong>verter, or the external loopback through the sample rate c<strong>on</strong>verter as <str<strong>on</strong>g>in</str<strong>on</strong>g>dicated <str<strong>on</strong>g>in</str<strong>on</strong>g> Table 2.<br />
Note: Take note that <str<strong>on</strong>g>in</str<strong>on</strong>g> this reference design, the received audio embedded <str<strong>on</strong>g>SDI</str<strong>on</strong>g> data and the transmitter<br />
clock doma<str<strong>on</strong>g>in</str<strong>on</strong>g> <str<strong>on</strong>g>in</str<strong>on</strong>g> the <str<strong>on</strong>g>SDI</str<strong>on</strong>g> duplex <str<strong>on</strong>g>in</str<strong>on</strong>g>stance are <str<strong>on</strong>g>in</str<strong>on</strong>g> the same clock doma<str<strong>on</strong>g>in</str<strong>on</strong>g> . You can transmit the<br />
looped back audio data <str<strong>on</strong>g>in</str<strong>on</strong>g>to the audio embed block directly without go<str<strong>on</strong>g>in</str<strong>on</strong>g>g through the sample<br />
rate c<strong>on</strong>verter. If the received audio embedded <str<strong>on</strong>g>SDI</str<strong>on</strong>g> data and the transmitter <str<strong>on</strong>g>in</str<strong>on</strong>g> the <str<strong>on</strong>g>SDI</str<strong>on</strong>g> duplex<br />
<str<strong>on</strong>g>in</str<strong>on</strong>g>stance are <str<strong>on</strong>g>in</str<strong>on</strong>g> different clock doma<str<strong>on</strong>g>in</str<strong>on</strong>g>s, you must pass the audio data through the sample rate<br />
c<strong>on</strong>verter before transmitt<str<strong>on</strong>g>in</str<strong>on</strong>g>g to the audio embed block.<br />
Test<str<strong>on</strong>g>in</str<strong>on</strong>g>g the <str<strong>on</strong>g>SDI</str<strong>on</strong>g> Transmitter with Embedded <str<strong>on</strong>g>Audio</str<strong>on</strong>g><br />
To test the <str<strong>on</strong>g>SDI</str<strong>on</strong>g> transmitter with an embedded audio, do the follow<str<strong>on</strong>g>in</str<strong>on</strong>g>g steps.<br />
<strong>Altera</strong> Corporati<strong>on</strong><br />
<str<strong>on</strong>g>Implement<str<strong>on</strong>g>in</str<strong>on</strong>g>g</str<strong>on</strong>g> <str<strong>on</strong>g>Audio</str<strong>on</strong>g> <str<strong>on</strong>g>IP</str<strong>on</strong>g> <str<strong>on</strong>g>in</str<strong>on</strong>g> <str<strong>on</strong>g>SDI</str<strong>on</strong>g> <str<strong>on</strong>g>II</str<strong>on</strong>g> <strong>on</strong> <strong>Arria</strong> V <strong>Development</strong> <strong>Board</strong><br />
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