Implementing Audio IP in SDI II on Arria V Development Board - Altera

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Clock Doma<strong>in</strong> and Data Paths
Figure 1: Block Diagram
AN-697
2013-12-20
Video Pattern
Generator P0
Ancillary Data
Insertion P0
<strong>Audio</strong> Pattern
Generator
<strong>Audio</strong> Embed P0
<strong>SDI</strong> <strong>II</strong> TX P0
<strong>SDI</strong>_OUT_2
Transceiver
Reconfiguration
<strong>SDI</strong> Duplex
AES_OUT_1
AES Output
Module
<strong>Audio</strong> Extract
RX
<strong>SDI</strong>_IN_1
Clocked <strong>Audio</strong>
Input
Clocked <strong>Audio</strong>
Output
AES_IN_1
AES Input
Module
<strong>Audio</strong> Embed P1
TX P1
<strong>SDI</strong>_OUT_1
<strong>Audio</strong> Sample
Rate Converter
Video Pattern
Generator P1
Ancillary Data
Insertion P1
Video data
<strong>Audio</strong> data
<strong>Audio</strong> Embedded <strong>SDI</strong> data
Reconfiguration Control data
Clock Doma<strong>in</strong> and Data Paths
The follow<strong>in</strong>g figures show the clock doma<strong>in</strong> and data paths for the <strong>SDI</strong> channels.
Altera Corporation
<strong>Implement<strong>in</strong>g</strong> <strong>Audio</strong> <strong>IP</strong> <strong>in</strong> <strong>SDI</strong> <strong>II</strong> on Arria V Development Board
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