Implementing Audio IP in SDI II on Arria V Development Board - Altera

More documents

Recommendations

Info

4 Reference Design Components Figure 3: Clock Doma<strong>in</strong> and Data Path for <strong>SDI</strong> Duplex Channel AN-697 2013-12-20 gxb_refclk (148.5/148.35 MHz) AES Output PIN gp_clk (125 MHz) rx_p1_clkout Aud PLL Aud PLL 1001 Clocked <strong>Audio</strong> Input Extracted audio data <strong>Audio</strong> Extract Transceiver Reconfig AES Input PIN <strong>Audio</strong> Sample Rate Converter Clocked <strong>Audio</strong> Output <strong>SDI</strong> RX ref_clk (100 MHz) Master PLL <strong>SDI</strong> RX Protocol <strong>SDI</strong> RX PHY <strong>SDI</strong> RX PIN Embedded data <strong>Audio</strong> data Video data <strong>Audio</strong> Embed <strong>SDI</strong> <strong>Audio</strong> Adaptor <strong>SDI</strong> TX Protocol <strong>SDI</strong> TX PHY <strong>SDI</strong> TX PIN gxb_refclk (148.5/148.35 MHz) <strong>SDI</strong> PLL Video Pattern Generator tx_p1_clkout <strong>SDI</strong> TX gxb_refclk (148.5/148.35 MHz) 100 MHz master PLL clock doma<strong>in</strong> (ref_clk) 148.5/148.35 MHz transceiver clock doma<strong>in</strong> (gxb_refclk) <strong>SDI</strong> TX P1 output clock doma<strong>in</strong> (tx_p1_clkout) <strong>SDI</strong> RX P1 output clock doma<strong>in</strong> (rx_p1_clkout) 125 MHz Reconfig clock (gp_clk) Data path Reference Design Components The follow<strong>in</strong>g sections describe the components <strong>in</strong> the reference design. <strong>Audio</strong> Embed The <strong>Audio</strong> Embed <strong>IP</strong> embeds the audio data <strong>in</strong>to SD, HD, and 3G <strong>SDI</strong>. The <strong>in</strong>put can be either synchronous or asynchronous to the video. However, the audio pairs embedded together <strong>in</strong> the same audio group must be synchronous to each other. <strong>Audio</strong> Extract The <strong>Audio</strong> Extract <strong>IP</strong> extracts the audio data from SD, HD, and 3G <strong>SDI</strong>. It can extract one channel pair of SD, HD, or 3G embedded audio. To extract more than one channel pair, multiple <strong>in</strong>stances of the <strong>IP</strong> are required. Clocked <strong>Audio</strong> Input The Clocked <strong>Audio</strong> Input <strong>IP</strong> converts the AES clocked audio to the Avalon-ST format. Clocked <strong>Audio</strong> Output The Clocked <strong>Audio</strong> Output <strong>IP</strong> accepts the clocked Avalon-ST audio and converts it to AES formats. Altera Corporation <strong>Implement<strong>in</strong>g</strong> <strong>Audio</strong> <strong>IP</strong> <strong>in</strong> <strong>SDI</strong> <strong>II</strong> on Arria V Development Board Feedback
AN-697 2013-12-20 <strong>Audio</strong> Sample Rate Converter The <strong>Audio</strong> Sample Rate Converter changes the audio sample rate without affect<strong>in</strong>g the phase or quality. This conversion is required for the <strong>Audio</strong> Embed <strong>IP</strong> to embed the audio from different sources with asynchronous clocks doma<strong>in</strong> that run at a different sample rate. <strong>SDI</strong> <strong>II</strong> Transmitter The triple-standard <strong>SDI</strong> <strong>II</strong> transmitter generates the embedded audio <strong>SDI</strong> signal <strong>in</strong> SD, HD, or 3G standard. The transmitter sends the audio signal <strong>in</strong> either NTSC or PAL format. <strong>SDI</strong> <strong>II</strong> Duplex Transceiver The triple-standard <strong>SDI</strong> <strong>II</strong> MegaCore function receives data <strong>in</strong> SD-<strong>SDI</strong>, HD-<strong>SDI</strong>, or 3G-<strong>SDI</strong> standard and performs receiver-to-transmitter loopback. The transceiver decodes, buffers, recodes, and then transmits the received data. The data can be <strong>in</strong> either NTSC or PAL format. Transceiver Reconfiguration The Transceiver reconfiguration control logic is required for the triple standard handl<strong>in</strong>g. This control logic reconfigures the receiver of the duplex core for different <strong>in</strong>com<strong>in</strong>g <strong>SDI</strong> data rates. Video Pattern Generator The video pattern generator generates the video pattern for different video formats such as 2.970-Gbps 1080p, 1.485-Gbps 1080i and 270-Mbps video patterns. The video test pattern is 100% color bar. Ancillary Data This block <strong>in</strong>serts the ancillary data <strong>in</strong>to the generated video pattern. The ancillary data <strong>in</strong>serted <strong>in</strong>cludes Check Sum Word (CS), Data Count Word (DC) and Data Identification Word (DID/<strong>SDI</strong>D). <strong>Audio</strong> Tone Generator The audio tone generator generates the audio <strong>in</strong>formation us<strong>in</strong>g an <strong>in</strong>crement<strong>in</strong>g counter. This audio data cannot be translated <strong>in</strong>to any audible sound. The data is for the audio pattern observation <strong>in</strong> the audio bar us<strong>in</strong>g the <strong>SDI</strong> signal analyzer <strong>in</strong> embedded audio mode <strong>in</strong> an <strong>in</strong>creas<strong>in</strong>g manner. If you want to test us<strong>in</strong>g audible audio data, you can use the test audio s<strong>in</strong>e wave pattern <strong>in</strong> the <strong>Audio</strong> Embed <strong>IP</strong>. <strong>SDI</strong> <strong>Audio</strong> Adaptor The <strong>SDI</strong> audio adaptor synchronizes the audio embedded <strong>SDI</strong> data between different clock doma<strong>in</strong>s. Related Information <strong>Audio</strong> Sample Rate Converter • Serial Digital Interface (<strong>SDI</strong>) User Guide For more <strong>in</strong>formation about <strong>Audio</strong> Embed, <strong>Audio</strong> Extract, Clocked <strong>Audio</strong> Input, and Clocked <strong>Audio</strong> Output <strong>IP</strong>s, refer to the Serial Digital Interface (<strong>SDI</strong>) User Guide. • <strong>Audio</strong> Sample Rate Converter For more <strong>in</strong>formation about the audio sample rate converter, refer to <strong>Audio</strong> Sample Rate Converter page. • Altera Transceiver PHY <strong>IP</strong> Core User Guide For more <strong>in</strong>formation about transceiver reconfiguration, refer to the Transceiver Reconfiguration Controller section <strong>in</strong> the Altera Transceiver PHY <strong>IP</strong> User Guide. 5 <strong>Implement<strong>in</strong>g</strong> <strong>Audio</strong> <strong>IP</strong> <strong>in</strong> <strong>SDI</strong> <strong>II</strong> on Arria V Development Board Altera Corporation Feedback
Page 1 and 2: 2013-12-20 Implement<strong
Page 3: AN-697 2013-12-20 Figure 2: Clock D
Page 7 and 8: AN-697 2013-12-20 Figure 5: <strong
Page 9 and 10: AN-697 2013-12-20 Runnin</s
Page 11 and 12: AN-697 2013-12-20 Testin</s

Implementing Audio IP in SDI II on Arria V Development Board - Altera

Create successful ePaper yourself

Delete template?

Save as template?