Implementing Audio IP in SDI II on Arria V Development Board - Altera

8
Runn<strong>in</strong>g the Reference Design
Table 2: Functions of D<strong>IP</strong> Switch Controls
AN-697
2013-12-20
7
6
5
4
3
2
1
0
Bit
Board Reference
SW3.8
SW3.7
SW3.6
SW3.5
SW3.4
SW3.3
SW3.2
SW3.1
Unused
Unused
Unused
Description
1: Indicate the <strong>in</strong>com<strong>in</strong>g video is <strong>in</strong> NTSC format (1/1.001
data rate)
0: Indicate the <strong>in</strong>com<strong>in</strong>g video is <strong>in</strong> PAL format
1: Loopback audio data pass<strong>in</strong>g through sample rate
converter
0: Loopback audio data depend<strong>in</strong>g on sett<strong>in</strong>g <strong>in</strong> D<strong>IP</strong> switch
bit 2 (SW3.3)
1: <strong>Audio</strong> data looped back <strong>in</strong>ternally through Clocked
<strong>Audio</strong> Input and Clocked <strong>Audio</strong> Output <strong>IP</strong>s
0: <strong>Audio</strong> data looped back externally without go<strong>in</strong>g through
converted sample rate
Indicates the <strong>SDI</strong> video standard:
00: SD
01: HD
10: 3GB
11: 3GA
Table 3: Functions of Push Buttons
PB0
PB1
PB2
Push Button
Reset
Unused
Unused
Description
Runn<strong>in</strong>g the Reference Design
To run the reference design, do the follow<strong>in</strong>g steps.
1. Set up the board connections.
a. Connect the <strong>SDI</strong> HSMC to the HSMC Port B of FPGA development board.
b. Specify the follow<strong>in</strong>g board sett<strong>in</strong>gs located on the back of the FPGA development board:
Altera Corporation
<strong>Implement<strong>in</strong>g</strong> <strong>Audio</strong> <strong>IP</strong> <strong>in</strong> <strong>SDI</strong> <strong>II</strong> on Arria V Development Board
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