LDPC Decoding: VLSI Architectures and Implementations
LDPC Decoding: VLSI Architectures and Implementations
LDPC Decoding: VLSI Architectures and Implementations
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<strong>LDPC</strong> <strong>Decoding</strong>, Quick Recap 1/5<br />
Bit nodes (also called variable nodes) correspond to received bits.<br />
Check nodes describe the parity equations of the transmitted bits.<br />
eg. v1+v4+v7= 0; v2+v5+v8 =0 <strong>and</strong> so on.<br />
The decoding is successful when all the parity checks are satisfied (i.e. zero).<br />
Flash Memory Summit 2013<br />
Santa Clara, CA 3
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