LDPC Decoding: VLSI Architectures and Implementations
LDPC Decoding: VLSI Architectures and Implementations
LDPC Decoding: VLSI Architectures and Implementations
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Some of architecture variations,<br />
1/5, sub-circulant processing<br />
700<br />
FIG. 7<br />
FS REGISTERS<br />
SIGN FIFO<br />
728<br />
LAYER 1 R LAYER 1<br />
LAYER 2 SELECT LAYER 2<br />
CONTROL LAYER 3<br />
LAYER 3<br />
512<br />
LAYER 4 516 LAYER 4<br />
504<br />
R OLD<br />
510<br />
CHANNEL LLR<br />
Q-FIFO<br />
724<br />
Q SUBTRACTOR -<br />
DOUBLE<br />
SIGN BIT 730<br />
+<br />
ARRAY<br />
BUFFERED<br />
CURRENT<br />
+<br />
508 LAYER PS<br />
714<br />
MxM<br />
PERMUTER<br />
718<br />
Q SHIFT<br />
506<br />
P<br />
BUFFER<br />
P<br />
+<br />
+<br />
CNU<br />
1-M<br />
702<br />
R NEW<br />
+<br />
P SUM<br />
ADDER ARRAY<br />
720<br />
726<br />
Flash Memory Summit 2013<br />
Santa Clara, CA 45