LDPC Decoding: VLSI Architectures and Implementations
LDPC Decoding: VLSI Architectures and Implementations
LDPC Decoding: VLSI Architectures and Implementations
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Architecture Variations, 4/5<br />
1300<br />
FIG. 13<br />
1328<br />
CONTROL<br />
1304<br />
Q SUBTRACTOR<br />
ARRAY<br />
1314<br />
FS MEMORY<br />
LAYER 1<br />
LAYER 2<br />
LAYER m-1<br />
-<br />
+<br />
+<br />
CYCLIC<br />
SHIFTER<br />
MUX<br />
1330<br />
R<br />
SELECT<br />
1312<br />
1316<br />
R OLD 1310<br />
Q FIFO<br />
1324<br />
Q SHIFT<br />
1306<br />
1318<br />
P<br />
1320<br />
P MEMORY<br />
DOUBLE<br />
BUFFERED<br />
+<br />
Q SIGN BIT<br />
1308<br />
1302<br />
CNU<br />
ARRAY<br />
+<br />
SIGN MEMORY<br />
LAYER 1<br />
LAYER 2<br />
LAYER m-1<br />
1326<br />
R NEW<br />
+<br />
P SUM<br />
ADDER ARRAY<br />
CHANNEL LLR<br />
Flash Memory Summit 2013<br />
Santa Clara, CA 48
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