LDPC Decoding: VLSI Architectures and Implementations

Block Parallel Layered Decoder
Compared to other work, this work has several advantages
1) Only one memory for holding the P values.
2) Shifting is achieved through memory reads. Only one
memory multiplexer network is needed instead of 2 to achieve
delta shifts
1) Value-reuse is effectively used for both Rnew and Rold
2) Low complexity data path design-with no redundant data
Path operations.
5) Low complexity CNU design with high parallelism.
6) Smaller pipeline depth
Here M is the row parallelization (i.e. number of rows in H matrix
Processed per clock).
Flash Memory Summit 2013
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