LDPC Decoding: VLSI Architectures and Implementations
LDPC Decoding: VLSI Architectures and Implementations
LDPC Decoding: VLSI Architectures and Implementations
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References [Contd]<br />
& Important Information<br />
• Several features presented in the Module 2 by Kiran Gunnam<br />
are covered by the following pending patent applications by<br />
Texas A&M University System (TAMUS).<br />
[P1] K. K. Gunnam <strong>and</strong> G. S. Choi, “Low Density Parity Check<br />
Decoder for Regular <strong>LDPC</strong> Codes,” U.S. Patent Application No.<br />
12/113,729, Publication No. US 2008/0276156 A1<br />
[P2] K. K. Gunnam <strong>and</strong> G. S. Choi, “Low Density Parity Check<br />
Decoder for Irregular <strong>LDPC</strong> Codes,” U.S. Patent Application No.<br />
12/113,755, Publication No. US 2008/0301521 A1<br />
Flash Memory Summit 2013<br />
Santa Clara, CA 51
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