ug900-vivado-logic-simulation

Chapter 2: Understanding Simulation Components in Vivado
It is important to note the following:
• You must specify different simulation libraries according to the simulation points.
• There are different gate-level cells in pre- and post-implementation netlists.
Table 2-2 lists the required simulation libraries at each simulation point.
Table 2-2:
Simulation Points and Relevant Libraries
Simulation Point UNISIM UNIFAST UNIMACRO SECUREIP
1. Register Transfer Level
(RTL) (Behavioral)
2. Post-Synthesis
Simulation (Functional)
3. Post-Synthesis
Simulation (Timing)
4. Post-Implementation
Simulation (Functional)
5. Post-Implementation
Simulation (Timing)
SIMPRIM
(Verilog Only)
IMPORTANT: The Vivado simulator uses precompiled simulation device libraries. When updates to
libraries are installed the precompiled libraries are automatically updated.
SDF
Yes Yes Yes Yes N/A No
Yes Yes N/A Yes N/A N/A
N/A N/A N/A Yes Yes Yes
Yes Yes N/A Yes N/A N/A
N/A N/A N/A Yes Yes Yes
Table 2-3:
Library
Note: Verilog SIMPRIMS_VER uses the same source as UNISIM with the addition of specify blocks
for timing annotation. SIMPRIMS_VER is the logical library name to which the Verilog physical
SIMPRIM is mapped.
Table 2-3 lists the library locations.
Simulation Library Locations
HDL
Type
Location
UNISIM Verilog /data/verilog/src/unisims
VHDL
/data/vhdl/src/unisims
UNIFAST Verilog /data/verilog/src/unifast
VHDL
/data/vhdl/src/unifast
UNIMACRO Verilog /data/verilog/src/unimacro
VHDL
/data/vhdl/src/unimacro
SECUREIP Verilog /data/secureip/secureip_cell.list.f.
The following subsections describe the libraries in more detail.
Logic Simulation www.xilinx.com
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UG900 (v2014.1) April 23, 2014