ug900-vivado-logic-simulation

Chapter 1
Logic Simulation Overview
Introduction
Simulation is a process of emulating the real design behavior in a software environment.
Simulation helps verify the functionality of a design by injecting stimulus and observing the
design outputs.
This chapter provides an overview of the simulation process, and the simulation options in
the Vivado ® Design Suite. The Vivado Design Suite Integrated Design Environment (IDE)
provides an integrated simulation environment when using the Vivado simulator.
For more information about the Vivado IDE and the Vivado Design Suite flow, see:
• Vivado Design Suite User Guide: Using the Vivado IDE (UG893) [Ref 2]
• Vivado Design Suite User Guide: Design Flows Overview (UG892) [Ref 9]
Simulation Flow
Simulation can be applied at several points in the design flow. It is one of the first steps
after design entry and one of the last steps after implementation as part of the verifying the
end functionality and performance of the design.
Simulation is an iterative process and is typically repeated until both the design
functionality and timing requirements are satisfied.
Logic Simulation www.xilinx.com
Send Feedback
6
UG900 (v2014.1) April 23, 2014