ug900-vivado-logic-simulation

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Chapter 2: Understanding Simulation Components in Vivado • Force a delta delay by using a temporary signal, as shown in the following example: clk_b
Chapter 2: Understanding Simulation Components in Vivado Disabling X Propagation for Synchronous Elements When a timing violation occurs during a timing simulation, the default behavior of a latch, register, RAM, or other synchronous elements is to output an X to the simulator. This occurs because the actual output value is not known. The output of the register could: • Retain its previous value • Update to the new value • Go metastable, in which a definite value is not settled upon until some time after the clocking of the synchronous element Because this value cannot be determined, and accurate simulation results cannot be guaranteed, the element outputs an X to represent an unknown value. The X output remains until the next clock cycle in which the next clocked value updates the output if another violation does not occur. The presence of an X output can significantly affect simulation. For example, an X generated by one register can be propagated to others on subsequent clock cycles. This can cause large portions of the design under test to become unknown. Correcting X-Generation To correct X-generation: • On a synchronous path, analyze the path and fix any timing problems associated with this or other paths to ensure a properly operating circuit. • On an asynchronous path, if you cannot otherwise avoid timing violations, disable the X propagation on synchronous elements during timing violations by the method described in Using the ASYNC_REG Constraint, page 34. When X propagation is disabled, the previous value is retained at the output of the register. In the actual silicon, the register might have changed to the 'new' value. Disabling X propagation might yield simulation results that do not match the silicon behavior. CAUTION! Exercise care when using this option. Use it only if you cannot otherwise avoid timing violations. Simulating Configuration Interfaces This section describes the simulation of the following configuration interfaces: • JTAG simulation • SelectMAP simulation Logic Simulation www.xilinx.com Send Feedback 35 UG900 (v2014.1) April 23, 2014
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Page 3 and 4: Table of Contents Chapter 1: Logic
Page 5 and 6: Simulating Xilinx Designs using Que
Page 7 and 8: Chapter 1: Logic Simulation Overvie
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Page 11 and 12: Chapter 2 Understanding Simulation
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Page 41 and 42: Chapter 3 Using the Vivado Simulato
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Chapter 4: Analyzing with the Vivad
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Chapter 5 Using Vivado Simulator Co
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Chapter 5: Using Vivado Simulator C
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Chapter 6: Debugging a Design with
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Chapter 7 Simulating with QuestaSim
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Chapter 7: Simulating with QuestaSi
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Chapter 8: Simulating with Cadence
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Chapter 9 Simulating with Synopsys
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Chapter 9: Simulating with Synopsys
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Appendix A: Value Rules in Vivado S
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Appendix B: Vivado Simulator Mixed
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Appendix C: Vivado Simulator Quick
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Appendix C: Vivado Simulator Quick
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Appendix D: SystemVerilog Construct
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Appendix E Additional Resources and
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ug900-vivado-logic-simulation

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