ug900-vivado-logic-simulation

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Revision History The following table shows the revision history for this document. Date Version Revision 04/23/2014 2014.1 Coded example for running a post-synthesis functional <strong>simulation</strong> from the command line corrected, page 112. Corrected information about switches in the section Compiling Simulation Libraries for VCS, page 149. Updated usage information on VCS Script Simulation, page 152. Added Appendix D, SystemVerilog Constructs Supported by the Vivado Simulator (early access). IDS_lite is obsolete; references to it have been removed. General updates made to reflect changes in version 2014.1, including SystemVerilog information, updates to graphics. Revisions and enhancements throughout, including updates to cross references and citations; addition of instructions on locating and displaying GUI features. Logic Simulation www.xilinx.com Send Feedback 2 UG900 (v2014.1) April 23, 2014
Table of Contents Chapter 1: Logic Simulation Overview Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Simulation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Supported Simulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Language and Encryption Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 OS Support and Release Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 2: Understanding Simulation Components in Vivado Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Using Test Benches and Stimulus Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Using Xilinx Simulation Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Compiling Simulation Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Understanding the Simulator Language Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Using the export_<strong>simulation</strong> Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Recommended Simulation Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Generating a Netlist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Annotating the SDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Using Global Reset and 3-State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Delta Cycles and Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Using the ASYNC_REG Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Simulating Configuration Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Disabling Block RAM Collision Checks for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Dumping the Switching Activity Interchange Format File for Power Analysis . . . . . . . . . . . . . . . . 40 Chapter 3: Using the Vivado Simulator from the Vivado IDE Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Vivado Simulator Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Adding or Creating Simulation Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Running the Vivado Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Running Post-Synthesis Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Running Post-Implementation Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Identifying Between Multiple Simulation Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Pausing a Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Logic Simulation www.xilinx.com Send Feedback 3 UG900 (v2014.1) April 23, 2014
Page 1: Vivado Design Suite User Guide Logi
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Chapter 3: Using the Vivado Simulat
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Chapter 5 Using Vivado Simulator Co
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Chapter 5: Using Vivado Simulator C
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Chapter 6: Debugging a Design with
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Chapter 7 Simulating with QuestaSim
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Chapter 8: Simulating with Cadence
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Chapter 9 Simulating with Synopsys
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Appendix A: Value Rules in Vivado S
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Appendix B: Vivado Simulator Mixed
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Appendix C: Vivado Simulator Quick
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Appendix D: SystemVerilog Construct
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Appendix E Additional Resources and
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