ug900-vivado-logic-simulation

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Chapter 2: Understanding Simulation Components in Vivado These primitives are contained in the following libraries: • UNISIMS_VER simulation library for Verilog simulation • UNISIMS simulation library for VHDL simulation In many cases, you can use the same test bench that you used for behavioral simulation to perform a more accurate simulation. The following Tcl commands generate Verilog and VHDL functional simulation netlist, respectively: write_verilog -mode funcsim write_vhdl -mode funcsim Generating a Timing Netlist You can use a Verilog timing simulation to verify circuit operation after the Vivado tools have calculated the worst-case placed and routed delays. In many cases, you can use the same test bench that you used for functional simulation to perform a more accurate simulation. Compare the results from the two simulations to verify that your design is performing as initially specified. There are two steps to generating a timing simulation netlist: 1. Generate a simulation netlist file for the design. 2. Generate an SDF delay file with all the timing delays annotated. IMPORTANT: Vivado IDE supports Verilog timing simulation only. The following is the syntax for generating a timing simulation netlist: • Tcl Command: write_verilog -mode timesim -sdf_anno true Annotating the SDF File Based on the specified process corner, the SDF file contains different min and max numbers. RECOMMENDED: Run two separate simulations to check for setup and hold violations. To run a setup check, create an SDF file with -process corner slow, and use the max column from the SDF file. Logic Simulation www.xilinx.com Send Feedback 30 UG900 (v2014.1) April 23, 2014
Chapter 2: Understanding Simulation Components in Vivado To run a hold check, create an SDF file with the -process corner fast, and use the min column from the SDF file. The method for specifying which SDF delay field to use is dependent on the simulation tool you are using. Refer to the specific simulation tool documentation for information on how to set this option. To get full coverage run all four timing simulations, specify as follows: ° Slow corner: SDFMIN and SDFMAX ° Fast corner: SDFMIN and SDFMAX Using Global Reset and 3-State Xilinx devices have dedicated routing and circuitry that connect to every register in the device. Global Set and Reset Net During configuration, the dedicated Global Set/Reset (GSR) signal is asserted. The GSR signal is deasserted upon completion of device configuration. All the flip-flops and latches receive this reset, and are set or reset depending on how the registers are defined. RECOMMENDED: Although you can access the GSR net after configuration, recommends avoiding use of the GSR circuitry in place of a manual reset. This is because the FPGA devices offer high-speed backbone routing for high fanout signals such as a system reset. This backbone route is faster than the dedicated GSR circuitry, and is easier to analyze than the dedicated global routing that transports the GSR signal. In post-synthesis and post-implementation simulations, the GSR signal is automatically asserted for the first 100 ns to simulate the reset that occurs after configuration. A GSR pulse can optionally be supplied in pre-synthesis functional simulations, but is not necessary if the design has a local reset that resets all registers. TIP: When you create a test bench, remember that the GSR pulse occurs automatically in the post-synthesis and post-implementation simulation. This holds all registers in reset for the first 100 ns of the simulation. Global 3-State Net In addition to the dedicated global GSR, output buffers are set to a high impedance state during configuration mode with the dedicated Global 3-state (GTS) net. All general-purpose outputs are affected whether they are regular, 3-state, or bidirectional Logic Simulation www.xilinx.com Send Feedback 31 UG900 (v2014.1) April 23, 2014
Page 1 and 2: Vivado Design Suite User Guide Logi
Page 3 and 4: Table of Contents Chapter 1: Logic
Page 5 and 6: Simulating Xilinx Designs using Que
Page 7 and 8: Chapter 1: Logic Simulation Overvie
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Page 11 and 12: Chapter 2 Understanding Simulation
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Page 41 and 42: Chapter 3 Using the Vivado Simulato
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Chapter 4: Analyzing with the Vivad
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Chapter 5 Using Vivado Simulator Co
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Chapter 5: Using Vivado Simulator C
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Chapter 6: Debugging a Design with
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Chapter 7 Simulating with QuestaSim
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Chapter 7: Simulating with QuestaSi
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Chapter 8: Simulating with Cadence
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Chapter 9 Simulating with Synopsys
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Chapter 9: Simulating with Synopsys
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Appendix A: Value Rules in Vivado S
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Appendix B: Vivado Simulator Mixed
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Appendix C: Vivado Simulator Quick
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Appendix C: Vivado Simulator Quick
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Appendix D: SystemVerilog Construct
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Appendix E Additional Resources and
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