ug900-vivado-logic-simulation

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Chapter 3: Using the Vivado Simulator from the Vivado IDE Adding or Creating Simulation Source Files To add simulation sources to a Vivado Design Suite project: 1. Select File > Add Sources, or click Add Sources. The Add Sources wizard opens. 2. Select Add or Create Simulation Sources, and click Next. The Add or Create Simulation Sources dialog box opens. The options are: ° Specify Simulation Set: Enter the name of the simulation set in which to store simulation sources (the default is sim_1, sim_2, and so forth). You can select the Create Simulation Set command from the drop-down menu to define a new simulation set. When more than one simulation set is available, the Vivado simulator shows which simulation set is the active (currently used) set. For a demonstration of this feature, see the Quick Take Video at www.xilinx.com/training/vivado/index.htm. ° Add Files: Invokes a file browser so you can select simulation source files to add to the project. ° Add Directories: Invokes directory browser to add all simulation source files from the selected directories. Files in the specified directory with valid source file extensions are added to the project. ° Create File: Invokes the Create Source File dialog box where you can create new simulation source files. See the Vivado Design Suite User Guide: Using the Vivado IDE (UG893) [Ref 2] for more information about project source files. ° Buttons on the side of the dialog box let you do the following: - Remove: Removes the selected source files from the list of files to be added. - Move Selected File Up: Moves the file up in the list order. - Move Selected File Down: Moves the file down in the list order. ° Check boxes in the wizard provide the following options: - Scan and add RTL include files into project: Scans the added RTL file and adds any referenced include files. - Copy sources into project: Copies the original source files into the project and uses the local copied version of the file in the project. Logic Simulation www.xilinx.com Send Feedback 42 UG900 (v2014.1) April 23, 2014
Chapter 3: Using the Vivado Simulator from the Vivado IDE If you elected to add directories of source files using the Add Directories command, the directory structure is maintained when the files are copied locally into the project. - Add sources from subdirectories: Adds source files from the subdirectories of directories specified in the Add Directories option. - Include all design sources for simulation: Includes all the design sources for simulation. Working with Simulation Sets The Vivado IDE stores simulation source files in simulation sets that display in folders in the Sources window, and are either remotely referenced or stored in the local project directory. The simulation set lets you define different sources for different stages of the design. For example, there can be one test bench source to provide stimulus for behavioral simulation of the elaborated design or a module of the design, and a different test bench to provide stimulus for timing simulation of the implemented design. When adding simulation sources to the project, you can specify which simulation source set to use. To edit a simulation set: 1. In the Sources window popup menu, select Simulation Sources > Edit Simulation Sets, as shown in Figure 3-1. X-Ref Target - Figure 3-1 Figure 3-1: Edit Simulation Sets Option The Add or Create Simulation Sources wizard opens. Logic Simulation www.xilinx.com Send Feedback 43 UG900 (v2014.1) April 23, 2014
Page 1 and 2: Vivado Design Suite User Guide Logi
Page 3 and 4: Table of Contents Chapter 1: Logic
Page 5 and 6: Simulating Xilinx Designs using Que
Page 7 and 8: Chapter 1: Logic Simulation Overvie
Page 9 and 10: Chapter 1: Logic Simulation Overvie
Page 11 and 12: Chapter 2 Understanding Simulation
Page 13 and 14: Chapter 2: Understanding Simulation
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Chapter 5 Using Vivado Simulator Co
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Chapter 5: Using Vivado Simulator C
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Chapter 6: Debugging a Design with
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Chapter 7 Simulating with QuestaSim
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Chapter 7: Simulating with QuestaSi
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Chapter 8: Simulating with Cadence
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Chapter 9 Simulating with Synopsys
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Chapter 9: Simulating with Synopsys
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Appendix A: Value Rules in Vivado S
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Appendix B: Vivado Simulator Mixed
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Appendix C: Vivado Simulator Quick
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Appendix C: Vivado Simulator Quick
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Appendix D: SystemVerilog Construct
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Appendix E Additional Resources and
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