ug900-vivado-logic-simulation

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Chapter 2: Understanding Simulation Components in Vivado During the BIT file download, the model processes each command and changes registers settings that mirror the hardware changes. You can monitor the CRC register as it actively accumulates a CRC value. The model also shows the Status Register bits being set as the device progresses through the different states of configuration. Debugging with the Model The SIM_CONFIGE2 model provides an example of a correct configuration. You can leverage this example to assist in the debug procedure if you encounter device programming issues. You can read the Status Register through JTAG using the Vivado Device Programmer tool. This register contains information relating to the current status of the device and is a useful debugging resource. If you encounter issues on the board, reading the Status Register in Vivado Device Programmer is one of the first debugging steps to take. After the status register is read, you can map it to the simulation to pinpoint the configuration stage of the device. For example, the GHIGH bit is set HIGH after the data load process completes successfully; if this bit is not set, then the data loading operation did not complete. You can also monitor the GTW, GWE, and DONE signals set in BitGen that are released in the start-up sequence. The SIM_CONFIGE2 model also allows for error injection. The active CRC logic detects any issue if the data load is paused and started again with any problems. It also detects bit flips manually inserted in the BIT file, and handles them just as the device would handle this error. Feature Support Each device-specific configuration user guide outlines the supported methods of interacting with each configuration interface.The table below shows which features discussed in the configuration user guides are supported. The SIM_CONFIGE2 model: • Does not support Readback of configuration data. • Does not store configuration data provided, although it does calculate a CRC value. • Can perform Readback on specific registers only to ensure that a valid command sequence and signal handling is provided to the device. • Is not intended to allow Readback data files to be produced. Logic Simulation www.xilinx.com Send Feedback 38 UG900 (v2014.1) April 23, 2014
Chapter 2: Understanding Simulation Components in Vivado Table 2-8: Model-Supported Slave SelectMAP and Serial Features Slave SelectMAP and Serial Features Supported Master mode No Daisy chain - slave parallel daisy chains No SelectMAP data loading Continuous SelectMAP data loading Non-continuous SelectMAP data loading SelectMAP ABORT SelectMAP reconfiguration SelectMAP data ordering Reconfiguration and MultiBoot Configuration CRC – CRC checking during configuration Configuration CRC – post-configuration CRC Yes Yes Yes Yes No Yes No Yes No Disabling Block RAM Collision Checks for Simulation Xilinx block RAM memory is a true dual-port RAM where both ports can access any memory location at any time. Be sure that the same address space is not accessed for reading and writing at the same time. This causes a block RAM address collision. These are valid collisions, because the data that is being read from the read port is not valid. In the hardware, the value that is read might be the old data, the new data, or a combination of the old data and the new data. In simulation, this is modeled by outputting X because the value read is unknown. For more information on block RAM collisions, see the user guide for the device. In certain applications, this situation cannot be avoided or designed around. In these cases, the block RAM can be configured not to look for these violations. This is controlled by the generic (VHDL) or parameter (Verilog) SIM_COLLISION_CHECK string in block RAM primitives. Logic Simulation www.xilinx.com Send Feedback 39 UG900 (v2014.1) April 23, 2014
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Chapter 4: Analyzing with the Vivad
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Chapter 4: Analyzing with the Vivad
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Chapter 5 Using Vivado Simulator Co
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Chapter 5: Using Vivado Simulator C
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Chapter 6: Debugging a Design with
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Chapter 7 Simulating with QuestaSim
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Chapter 7: Simulating with QuestaSi
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Chapter 8: Simulating with Cadence
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Chapter 9 Simulating with Synopsys
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Chapter 9: Simulating with Synopsys
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Appendix A: Value Rules in Vivado S
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Appendix B: Vivado Simulator Mixed
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Appendix C: Vivado Simulator Quick
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Appendix C: Vivado Simulator Quick
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Appendix D: SystemVerilog Construct
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Appendix E Additional Resources and
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