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Parallelism: More economical with flatter cost structure 2X 3X 4X Run rate over 1X >1.x >2.x >>2.x • Parallelism is worth pursuing • Pick optimal level of parallelism – Benefits have not scaled previously because of disproportionate increase in SIU cost June 3-6, 3 2007 IEEE SW Test Workshop 18
Known Good Die Sort Correlation to Class OK (Today) Probe C4 bumps ???? Excellent (True KGD) • Environmental differences a challenge: – Thermal, electrical (packaging, xIU), content • Some can be addressed by improved SIU electrical capabilities June 3-6, 3 2007 IEEE SW Test Workshop 19
Page 1 and 2: Wafer level testing Challenges and
Page 3 and 4: Moore’s s Law: Our friend, our ch
Page 5 and 6: Test Cost Trends: Circa 1997 Each g
Page 7 and 8: 1. Developing New Tester Architectu
Page 9 and 10: Intel Test Cost Trends Today Intel
Page 11 and 12: But, going forward …. June 3-6, 3
Page 13 and 14: Disturbing trends re-emerging emerg
Page 15 and 16: Tooling >50% Sort cost Deprec. Labo
Page 17: Proof of concept of performance Pas
Page 21 and 22: ….. And don’t t forget • Lead
Page 23 and 24: Supplier and customer collaboration
Page 25: Q & A June 3-6, 3 2007 IEEE SW Test

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