Overcoming the Challenges of Parallel RF Test - Semiconductor ...

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• The Challenges • Roadblocks Outline • Clearing the Obstacles • Summary June 8 to 11, 2008 IEEE SW Test Workshop 2
The Challenges Decrease the cost to wafer-test RF devices • Cost to Test one die: Cost die ⎛ $ obeCard f ⎜ Pr + $ ⎝ Touchdowns * t = Station Test ⎞ ⎟ ⎠ • From this: – Increase Life of Probe card (more touchdowns). – Minimize Test Time. – Test more die per touchdown. • Setup: – You have “zero time” to debug the test program, after wafers arrive. • It’s all easy, right? June 8 to 11, 2008 IEEE SW Test Workshop 3
Page 1: Roger Hayward Cascade Microtech Ove
Page 5 and 6: • Known Good Die RF Test: The Cha
Page 7 and 8: Roadblocks • RF Calibration • R
Page 9 and 10: Roadblock #2 Are you measuring your
Page 11 and 12: Roadblock #3 Have you fully-optimiz
Page 13 and 14: Clearing the Obstacles • RF Calib
Page 15 and 16: • Measure 4 standards: - Short -
Page 17 and 18: Scalar RF Calibration Measure Short
Page 19 and 20: Clearing the Obstacles Cater your s
Page 25 and 26: Pyramid Accel Concept Enabling Para
Page 27 and 28: Pyramid Accel Fixture Enabling Para
Page 29: Summary Thank You! June 8 to 11, 20

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