Overcoming the Challenges of Parallel RF Test - Semiconductor ...

Roger Hayward
Cascade Microtech
Overcoming the Challenges
of
Parallel RF Test
June 8-11, 8
2008
San Diego, CA USA

• The Challenges
• Roadblocks
Outline
• Clearing the Obstacles
• Summary
June 8 to 11, 2008
IEEE SW Test Workshop 2

The Challenges
Decrease the cost to wafer-test RF devices
• Cost to Test one die:
Cost
die
⎛ $
obeCard
f ⎜
Pr + $
⎝ Touchdowns
* t
=
Station Test
⎞
⎟
⎠
• From this:
– Increase Life of Probe card (more touchdowns).
– Minimize Test Time.
– Test more die per touchdown.
• Setup:
– You have “zero time” to debug the test program, after wafers arrive.
• It’s all easy, right?
June 8 to 11, 2008
IEEE SW Test Workshop 3

• Known Good Die RF Test:
The Challenges
Example: SPDT RF Switch
– Confirm Operation.
– Verify:
• Low Insertion Loss (connected path)
• Isolation (disconnected path)
• Linearity (3 rd Harmonic)
• Consider testing in parallel:
– 1 die
.
June 8 to 11, 2008
IEEE SW Test Workshop 4

• Known Good Die RF Test:
The Challenges
Example: SPDT RF Switch
– Confirm Operation.
– Verify:
• Low Insertion Loss (connected path)
• Isolation (disconnected path)
• Linearity (3 rd Harmonic)
• Consider testing in parallel:
– 1 die
Meter
.
RF Source
June 8 to 11, 2008
IEEE SW Test Workshop 5

• Known Good Die RF Test:
The Challenges
Example: SPDT RF Switch
– Confirm Operation.
– Verify:
• Low Insertion Loss (connected path)
• Isolation (disconnected path)
• Linearity (3 rd Harmonic)
• Consider testing in parallel:
– 1 die
– 2 die
– 8 die?
RF Source
Meter
June 8 to 11, 2008
IEEE SW Test Workshop 6

Roadblocks
• RF Calibration
• RF Isolation
• Parallelism
• Multi-DUT Test Program Debug
• Wafer and Prober Availability
June 8 to 11, 2008
IEEE SW Test Workshop 7

Roadblock #1
Do you know the losses of your transmission path?
• RF Calibration
• All probes have path loss
– (Some have less than others).
• Characterize the loss
• Subtract from measurement
June 8 to 11, 2008
IEEE SW Test Workshop 8

Roadblock #2
Are you measuring your die or your probe card?
• RF Isolation
– Port-to-Port
– Die-to-Die
RF Source
Meter
June 8 to 11, 2008
IEEE SW Test Workshop 9

Roadblock #2
Are you measuring your die or your probe card?
• RF Isolation
– Port-to-Port
– Die-to-Die
RF Source
Meter
June 8 to 11, 2008
IEEE SW Test Workshop 10

Roadblock #3
Have you fully-optimized your test program?
Time
Insertion
Loss
Isolation
Insertion
Loss
Position 1 Position 2
Isolation
DUT 1
Insertion
Loss
Isolation
Insertion
Loss
Position 1 Position 2
Isolation
DUT 2
Insertion
Loss
Isolation
Insertion
Loss
Position 1 Position 2
Isolation
DUT 3
June 8 to 11, 2008
IEEE SW Test Workshop 11

Roadblock #4
Have you fully debugged your probe card?
• How much time do you have to optimize this program?
• How many wafers will you get to use?
• What is broken:
– The silicon?
– The test program?
– The probe card?
June 8 to 11, 2008
IEEE SW Test Workshop 12

Clearing the Obstacles
• RF Calibration:
– Vector
– Scalar
• Direct measurement
• Short-Open
Building your system
• Catering your system for Parallel Test
• Test Optimization
June 8 to 11, 2008
IEEE SW Test Workshop 13

RF Calibration
What is it?
• Probes have electrical loss.
• Measurements include the loss.
a 0 b 1
1
Γ m
ED
E R
ES
b 0 a 1
Γ a
• Calibration:
– Characterize the transmission path.
– Remove (de-embed) the loss from the
measurements.
Measurement
Probe Loss
E D
: Directivity
E S
: Source Match
E R
: Frequency Tracking
Actual Result
• Scalar Calibration:
– Magnitude loss only.
• Vector Calibration:
– Magnitude and phase.
Γ
m
=
E
D
ERΓa
+
1−
E Γ
S
a
June 8 to 11, 2008
IEEE SW Test Workshop 14

• Measure 4 standards:
– Short
– Open
– Load (50 ohms)
– Thru path between ports.
Vector RF Calibration
2-port techniques
• Disadvantages:
– Probe standards.
– Standards must match probe topology.
– VNA software required.
– Difficult to integrate within an ATE
environment.
– Vector calibration usually not required
for KGD test.
(A)
1ps thru path,
200um length
Shorting bars
50 ohm GSG loads
June 8 to 11, 2008
IEEE SW Test Workshop 15

Scalar RF Calibration
Simple characterization techniques
• Direct Measurement:
– Use two ports.
– Measure the loss, end-to-end.
– Divide loss by 2.
Probe Tips
Length-Matched Thru
• Implementation:
– Length-matched thru.
– Cal-thru.
– On-die thru.
June 8 to 11, 2008
IEEE SW Test Workshop 16

Scalar RF Calibration
Measure Short-Open to characterize RF path loss
• Directivity (E D
) and Source Match (E S
) are generally small.
• Probe Short, Open. Take average.
• Predicted loss is usually within 0.2dB @ 2 GHz
Γ m
a 0 b 1
ED
1
E R
ES
b 0 a 1
Measurement
Probe Loss
Actual Result
Γ
m
=
E
D
ERΓa
+
1−
E Γ
S
a
Γ a
Γ
Γ
m−Open
m−Short
Γ = 1
a
Γ
=
E
=
D
E
ER
+
1−
E
D
−
a =−1
1+
S
;
ER
E
S
E D
↓ 0;
E ↓
S
0;
Γ
m
=
E Γ
R
a
E R
Γ
=
m−Open
− Γ
2
m−Short
June 8 to 11, 2008
IEEE SW Test Workshop 17

Scalar RF Calibration
Measure Short-Open to characterize RF path loss
• Incorporate Shorting path into probe:
June 8 to 11, 2008
IEEE SW Test Workshop 18

Clearing the Obstacles
Cater your system for Parallel test
Time
Insertion
Loss
Isolation
Insertion
Loss
Isolation
Position 1 Position 2
Meter
RF Source
June 8 to 11, 2008
IEEE SW Test Workshop 19

Clearing the Obstacles
Cater your system for Parallel test
Time
Insertion
Loss
Isolation
Insertion
Loss
Isolation
Position 1 Position 2
RF Source
June 8 to 11, 2008
IEEE SW Test Workshop 20

Clearing the Obstacles
Cater your system for Parallel test
Time
Insertion
Loss
Isolation
Isolation
Insertion
Loss
Position 1 Position 2
RF Source
June 8 to 11, 2008
IEEE SW Test Workshop 21

Clearing the Obstacles
Cater your system for Parallel test
Time
Insertion
Loss
Isolation
Isolation
Insertion
Loss
Position 1 Position 2
Insertion
Loss
Isolation
Isolation
Insertion
Loss
Position 1 Position 2
RF Source
June 8 to 11, 2008
IEEE SW Test Workshop 22

Clearing the Obstacles
Cater your system for Parallel test
Time
Insertion
Loss
Isolation
Isolation
Insertion
Loss
Position 1 Position 2
Insertion
Loss
Isolation
Isolation
Insertion
Loss
Position 1 Position 2
Reduce Isolation requirements
by testing
at different frequencies.
RF Source
RF Source
June 8 to 11, 2008
IEEE SW Test Workshop 23

Debugging the Test Program
• Reality Check:
A significant challenge of Parallel RF Test
– Most devices are not as simple as this
example…
• Parallel Test Setup:
– Develop test without burning up wafers.
– Develop test with few wafers at a manual
station.
– Optimize test time.
– Assure complete test coverage of part.
June 8 to 11, 2008
IEEE SW Test Workshop 24

Pyramid Accel Concept
Enabling Parallel RF Test
• Design Test program.
• Design Probe card.
• Obtain blind-build packaged parts.
• Temporarily eliminate:
– Wafer prober (cost & availability)
– Wafers (develop prior to their arrival)
Pyramid Probe “Core”
Pyramid Accel Debug Fixture
• Test with packaged parts.
• Optimize test program.
June 8 to 11, 2008
IEEE SW Test Workshop 25

Pyramid Accel Fixture
June 8 to 11, 2008
IEEE SW Test Workshop 26

Pyramid Accel Fixture
Enabling Parallel RF Test
• Test features:
– Enables test of complex probe cards.
– Socket option allows you to replace
blind-build parts.
– Electrical performance similar to
Pyramid Probe performance.
Pyramid Probe Core
• Golden Probe:
– Keep an Accel fixture at the production
test site.
– Validate probe card & test program are
still functioning properly.
Pyramid Accel Debug Fixture
June 8 to 11, 2008
IEEE SW Test Workshop 27

Summary
Parallel RF Test presents a unique Challenge
• Calibrate RF path loss using scalar techniques.
• Characterize port-to-port isolation.
• Design probe card to optimize for parallel test.
• Write a true parallel-processing test program.
• Optimize your test program as early as
possible.
– Assure adequate test coverage.
– Lower your test cost per die.
June 8 to 11, 2008
IEEE SW Test Workshop 28

Summary
Thank You!
June 8 to 11, 2008
IEEE SW Test Workshop 29