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Dr. Tong Yan TEE Nepes, Singapore Dr. Tong Yan Tee has over 15 years of working experience in semiconductor industry, mainly on IC packaging in the areas of R&D management, capability development and strategic planning. He is Deputy R&D Director of Nepes Singapore, heading the R&D of 12-inch wafer bumping, wafer level packaging, and emerging technologies. Previously he has worked in Hewlett Packard, Institute of Microelectronics, STMicroelectronics, and Amkor Technology on various technical and management positions. Throughout his career, Dr. Tee has won 13 ST Corporate Awards for his achievement, 2 best paper awards, 6 US patents filed and over 150 publications in journals, conferences and book chapters. Dr. Tee is also a conference short course instructor, journal guest editor, IEEE Senior Member, and serves in the organizing and technical committees of several international conferences. He was the General Chair of EPTC 2008 conference. He is listed in Who’s Who in the World, 2007. Mr. Ming XUE Infineon, Singapore Mr. Ming Xue is the head of failure analysis lab of Infineon Asia Pacific. He obtained a degree in radio technology from Xi’an JiaoTong University, China in 1982. He started to work in Navigational Aids International, Shanghai in 1982, where he worked for 10 years as a product designer/project manager for products in radio receiver, radio transmitter, and wireless remote control system of navigational aids signal. In 1992, he joint Seagate technology international Singapore as a product engineer, and worked 4 years in PCBA process and FA lab. In 1995, he joint Siemens Component, now, Infineon Technologies Singapore as Senior FA engineer. Currently, he is senior manager of the failure analysis lab. In his 16 years semiconductor backend experience, his job involves IC chip and package failure analysis, package reliability characterization, process quality risk management, qualification, customer return and printed circuit board assembly support. He is listed in Who’s Who in Science and Engineering. OVERVIEW OF TSV / ITRS FORUM Monday, August 8, 2011 Venue Time Chairs Topic Speakers Room 3 (TSV) 13:00--13:30 3D Wafer Level System Integration 13:30--14:00 Dr. Wenhui Future Challenges in 3D-IC Packaging ZHU 14:00--14:30 TSV Key Technology for Next Generation Packaging Dr. Wolf JURGEN IZM, Germany Dr. Yasumitsu ORII IBM, Japan Dr. Frank LAI Qtech, China 14:30--15:00 Q & A 15:00--15:30 Coffee Break Speakers Room 3 (ITRS) 15:30--17:30 Dr. William CHEN Dr. Bill BOTTOM Dr. Bernd APPELT Prof. Ricky LEE Dr. Yishao LAI 3MTS, USA ASE, USA HKUST, HK, China ASE, Global, TW, China 12
Introduction of TSV Forum Speakers Dr. Wolf JURGEN IZM, Germany Dr. Wolf Juergen received a MS degree in Electrical Engineering. In 1994, he joined Fraunhofer Institute for Reliability and Micro integration (IZM), Berlin and has worked as group & project manager in the field of wafer level packaging and system-in-package (SiP). Since 2011 he is the head of department HDI&WLP/ASSID, responsible for the coordination and management of ASSID - “All Silicon System Integration Dresden-ASSID” with its 300 mm Wafer Level Integration. He manages as well as participates in a number of research projects on European and international level. He is an European representative in the technical working group Assembly & Packaging of ITRS, JEC, JIC and a board member of EURIPIDES as well as member of IEEE and SMTA. He has authored and co-authored more than 50 papers and holds a number of patents. Dr. Yasumitsu ORII IBM, Japan Dr. Yasumitsu Orii received a BS from Osaka University, Japan. He is a Senior Technical Staff Member working in 3D Integration for IBM Research Tokyo. He joined the IBM Japan in 1986. In 1996, he developed Flip Chip on FPC technique for IBM Hard Disk Drive to realize the enhancement of HDD performance and the slim form factor. Since 2003 he has started the development of ultra thin SiP/PoP for Digital Consumer Electronics Products and he developed C2 as a ultra fine pitch flip chip interconnection technique. In 2009, he was transferred to IBM Research Tokyo to focus on the development of 3D-IC packaging. Dr. Orii received an Excellent Research Award from the Micro Joining Committee of Japan Welding Society in 1996 and a Best Paper Award from ICEP-2008. He was a chair of Technical Program Committee of ICEP-2009 in Kyoto, ICEP-2010 in Sapporo and ICEP-2011 in Nara. He will be a general chair of ICEP-2012 in Tokyo. Dr. Frank LAI Q-technology, China Dr. Frank Lai is the VP engineer of Kunshan Q technology Ltd. He worked for Ambit Ltd as process engineer in 2002, and he entered Suzhou Walton technology Ltd as process section manager and product section manager from 2003 to 2007, then he worked for Q-technology limited till now. He has rich experience in module engineering, TSV package engineering and TSV package division. Introduction of ITRS International Technology Roadmap for Semiconductors (ITRS) serves as guideline for the global semiconductor industry, providing a 15 year outlook for 16 sectors of the industry and a 25 years projection of technology needs for emerging research devices and materials. As the industry moves into the era of More Moore and More than Moore, the role of ITRS is becoming even more crucial and critical for continuing progress. This workshop is conducted by the 2011 ITRS Assembly and Packaging working group, focusing on the major technology developments, difficult challenges, and potential solutions for the 2011 ITRS Assembly and Packaging Chapter. The coverage will include Au & Cu wire bond, flip chip BGA and flip chip CSP, wafer level packaging technologies, 3D and 2.5D TSV technology developments, as well as special applications including Optoelectronic Packaging, Automotive Electronics, and Medical Electronics. 13
Page 3 and 4: CONTENTS WELCOME FROM THE GENERAL C
Page 5 and 6: WELCOME FROM THE GENERAL CHAIR Star
Page 7 and 8: CONFERENCE CHAIRS( 大会主席
Page 9 and 10: Chiar for PDC & Forum Wenhui ZHU Se
Page 11 and 12: Prof. Yuming WANG Dr. Jianhua WU Dr
Page 13 and 14: OVERVIEW OF CONFERENCE PROGRAM( 会
Page 15: Dr. Yong LIU Fairchild, USA Dr. Yon
Page 19 and 20: Prof. C.P. WONG GT, USA Prof. C.P.
Page 21 and 22: Dr. Thorsten MATTHIAS EV Group, Aus
Page 23 and 24: Engineering at The University of To
Page 25 and 26: Chairs 08:00--09:20 OVERVIEW OF ORA
Page 27 and 28: ORAL SESSIONS Note: Only the contac
Page 29 and 30: Electromigration Behavior in In-sit
Page 31 and 32: Nepes, Singapore Session14: Advance
Page 33 and 34: University of Maryland, USA F-052 1
Page 35 and 36: Ziyang Wu, Chuanguo Dou, Yanhong Wu
Page 37 and 38: POSTER SESSION 1 Note: Only the con
Page 39 and 40: Model Zhao Wang 1 , Heming Zhao, We
Page 41 and 42: soldering reaction L. Y. Gu, L. Qu,
Page 43 and 44: Area 1 (Session G): Solid State Lig
Page 45 and 46: Area 5 (Session F): Quality & Relia
Page 47 and 48: 会议结束时间 :8 月 11
Page 49 and 50: TRANSPORTATION MAP 45

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