ARM PrimeCell Synchronous Serial Port (PL022) Technical ...

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Chapter 2 Functional Overview This chapter describes the major functional blocks of the ARM PrimeCell Synchronous Serial Port (PL022). It contains the following sections: • PrimeCell SSP overview on page 2-2 • PrimeCell SSP functional description on page 2-3 • PrimeCell SSP operation on page 2-6. ARM DDI 0194G Copyright © 2000-2001, 2009, 2011. All rights reserved. 2-1 ID110411 Non-Confidential
Functional Overview 2.1 PrimeCell SSP overview The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have Motorola SPI, National Semiconductor Microwire, or Texas Instruments synchronous serial interfaces. The PrimeCell SSP performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information through the AMBA APB interface. The transmit and receive paths are buffered with internal FIFO memories enabling up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The PrimeCell SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock, SSPCLKOUT, from the input clock, SSPCLK. Bit rates are supported to 2MHz and higher, subject to choice of frequency for SSPCLK, and the maximum bit rate is determined by peripheral devices. You can use the control registers SSPCR0 and SSPCR1 to program the PrimeCell SSP operating mode, frame format, and size. See Control register 0, SSPCR0 on page 3-4 and Control register 1, SSPCR1 on page 3-5. The following individually maskable interrupt outputs are generated: • SSPTXINTR requests servicing of the transmit buffer • SSPRXINTR requests servicing of the receive buffer • SSPRORINTR indicates an overrun condition in the receive FIFO • SSPRTINTR indicates that a timeout period expired while data was present in the receive FIFO. A single combined interrupt, SSPINTR output, is asserted if any of the individual interrupts are asserted and unmasked. In addition to the above interrupts, a set of DMA signals are provided for interfacing with a DMA controller. Depending on the operating mode selected, the SSPFSSOUT output operates as: • an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format • an active-LOW slave select for SPI and Microwire. ARM DDI 0194G Copyright © 2000-2001, 2009, 2011. All rights reserved. 2-2 ID110411 Non-Confidential
Page 1 and 2: ® ARM PrimeCell Synchronous Serial
Page 3 and 4: Contents ARM PrimeCell Synchronous
Page 5 and 6: Preface This preface introduces the
Page 7 and 8: Preface • Signals. Typographical
Page 9 and 10: Preface Additional reading This sec
Page 11 and 12: Chapter 1 Introduction This chapter
Page 13 and 14: Introduction • Internal loopback
Page 15: Introduction 1.2 Product revisions
Page 19 and 20: Functional Overview 2.2.1 AMBA APB
Page 21 and 22: Functional Overview 2.3 PrimeCell S
Page 23 and 24: Functional Overview The Serial Cloc
Page 25 and 26: Functional Overview SSPCLKOUT/ SSPC
Page 27 and 28: Functional Overview SSPCLKOUT/ SSPC
Page 29 and 30: Functional Overview However, in the
Page 31 and 32: Functional Overview Note The off-ch
Page 33 and 34: Functional Overview PL022 configure
Page 35 and 36: Functional Overview Table 2-1 shows
Page 37 and 38: Programmer’s Model 3.1 About the
Page 39 and 40: Programmer’s Model 3.3 Register d
Page 41 and 42: Programmer’s Model Table 3-3 show
Page 43 and 44: Programmer’s Model Table 3-5 show
Page 45 and 46: Programmer’s Model Table 3-7 SSPI
Page 47 and 48: Programmer’s Model 15 2 1 0 Reser
Page 49 and 50: Programmer’s Model SSPPeriphID0 r
Page 51 and 52: Programmer’s Model 15 8 7 0 Reser
Page 53 and 54: Programmer’s Model SSPPCellID2 re
Page 55 and 56: Programmer’s Model 3.4 Interrupts
Page 57 and 58: Chapter 4 Programmer’s Model for
Page 59 and 60: Programmer’s Model for Test 4.2 S
Page 61 and 62: Programmer’s Model for Test 4.3.2
Page 63 and 64: Programmer’s Model for Test Table
Page 65 and 66: Programmer’s Model for Test conne
Page 67 and 68:
Programmer’s Model for Test 4.5.2
Page 69 and 70:
Programmer’s Model for Test 4.6 I
Page 71 and 72:
Appendix A Signal Descriptions This
Page 73 and 74:
Signal Descriptions A.2 On-chip sig
Page 75 and 76:
Appendix B Revisions This appendix
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