ARM PrimeCell Synchronous Serial Port (PL022) Technical ...

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Programmer’s Model 15 0 Data Figure 3-3 SSPDR Register bit assignments Table 3-4 shows the bit assignments. Table 3-4 SSPDR Register bit assignments Bits Name Function [15:0] DATA Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. 3.3.4 Status register, SSPSR The SSPSR Register characteristics are: Purpose SSPSR is a RO status register that contains bits that indicate the FIFO fill status and the PrimeCell SSP busy status. Usage constraints There are no usage constraints. Configurations Available in all SSP configurations. Attributes See Table 3-1 on page 3-3. Figure 3-4 shows the bit assignments. 15 5 4 3 2 1 0 Reserved BSY RFF RNE TNF TFE Figure 3-4 SSPSR Register bit assignments ARM DDI 0194G Copyright © 2000-2001, 2009, 2011. All rights reserved. 3-7 ID110411 Non-Confidential
Programmer’s Model Table 3-5 shows the bit assignments. Table 3-5 SSPSR Register bit assignments Bits Name Function [15:5] - Reserved, read unpredictable, should be written as 0. [4] BSY PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [3] RFF Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. [2] RNE Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. [1] TNF Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. [0] TFE Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. 3.3.5 Clock prescale register, SSPCPSR The SSPCPSR Register characteristics are: Purpose SSPCPSR is the clock prescale register and specifies the division factor by which the input SSPCLK must be internally divided before further use. The value programmed into this register must be an even number between 2-254. The least significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least significant bit as zero. Usage constraints There are no usage constraints. Configurations Available in all SSP configurations. Attributes See Table 3-1 on page 3-3. Figure 3-5 shows the bit assignments. 15 8 7 0 Reserved CPSDVSR Figure 3-5 SSPCPSR Register bit assignments ARM DDI 0194G Copyright © 2000-2001, 2009, 2011. All rights reserved. 3-8 ID110411 Non-Confidential
Page 1 and 2: ® ARM PrimeCell Synchronous Serial
Page 3 and 4: Contents ARM PrimeCell Synchronous
Page 5 and 6: Preface This preface introduces the
Page 7 and 8: Preface • Signals. Typographical
Page 9 and 10: Preface Additional reading This sec
Page 11 and 12: Chapter 1 Introduction This chapter
Page 13 and 14: Introduction • Internal loopback
Page 15 and 16: Introduction 1.2 Product revisions
Page 17 and 18: Functional Overview 2.1 PrimeCell S
Page 19 and 20: Functional Overview 2.2.1 AMBA APB
Page 21 and 22: Functional Overview 2.3 PrimeCell S
Page 23 and 24: Functional Overview The Serial Cloc
Page 25 and 26: Functional Overview SSPCLKOUT/ SSPC
Page 27 and 28: Functional Overview SSPCLKOUT/ SSPC
Page 29 and 30: Functional Overview However, in the
Page 31 and 32: Functional Overview Note The off-ch
Page 33 and 34: Functional Overview PL022 configure
Page 35 and 36: Functional Overview Table 2-1 shows
Page 37 and 38: Programmer’s Model 3.1 About the
Page 39 and 40: Programmer’s Model 3.3 Register d
Page 41: Programmer’s Model Table 3-3 show
Page 45 and 46: Programmer’s Model Table 3-7 SSPI
Page 47 and 48: Programmer’s Model 15 2 1 0 Reser
Page 49 and 50: Programmer’s Model SSPPeriphID0 r
Page 51 and 52: Programmer’s Model 15 8 7 0 Reser
Page 53 and 54: Programmer’s Model SSPPCellID2 re
Page 55 and 56: Programmer’s Model 3.4 Interrupts
Page 57 and 58: Chapter 4 Programmer’s Model for
Page 59 and 60: Programmer’s Model for Test 4.2 S
Page 61 and 62: Programmer’s Model for Test 4.3.2
Page 63 and 64: Programmer’s Model for Test Table
Page 65 and 66: Programmer’s Model for Test conne
Page 67 and 68: Programmer’s Model for Test 4.5.2
Page 69 and 70: Programmer’s Model for Test 4.6 I
Page 71 and 72: Appendix A Signal Descriptions This
Page 73 and 74: Signal Descriptions A.2 On-chip sig
Page 75 and 76: Appendix B Revisions This appendix

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