ARM PrimeCell Synchronous Serial Port (PL022) Technical ...

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Chapter 3 Programmer’s Model This chapter describes the ARM PrimeCell Synchronous Serial Port (PL022) registers and provides details needed when programming the microcontroller. It contains the following sections: • About the programmer’s model on page 3-2 • Summary of PrimeCell SSP registers on page 3-3 • Register descriptions on page 3-4 • Interrupts on page 3-20. ARM DDI 0194G Copyright © 2000-2001, 2009, 2011. All rights reserved. 3-1 ID110411 Non-Confidential
Programmer’s Model 3.1 About the programmer’s model The following information applies to the Synchronous Serial Port (PL022) registers: • The base address is not fixed, and can be different for any particular system implementation. The offset of each register from the base address is fixed. • Do not attempt to access reserved or unused address locations. Attempting to access these locations can result in Unpredictable behavior. • Unless otherwise stated in the accompanying text: — do not modify undefined register bits — ignore undefined register bits on reads — all register bits are reset to a logic 0 by a system or power-on reset. • Access type in Table 3-1 on page 3-3 is described as follows: RW Read and write. RO Read only. WO Write only. The following locations are reserved, and must not be used during normal operation: • locations at offsets +0x028 to +0x07C and +0xFD0 to +0xFDC are reserved for possible future extensions • locations at offsets +0x080 to +0x088 are reserved for test purposes. ARM DDI 0194G Copyright © 2000-2001, 2009, 2011. All rights reserved. 3-2 ID110411 Non-Confidential
Page 1 and 2: ® ARM PrimeCell Synchronous Serial
Page 3 and 4: Contents ARM PrimeCell Synchronous
Page 5 and 6: Preface This preface introduces the
Page 7 and 8: Preface • Signals. Typographical
Page 9 and 10: Preface Additional reading This sec
Page 11 and 12: Chapter 1 Introduction This chapter
Page 13 and 14: Introduction • Internal loopback
Page 15 and 16: Introduction 1.2 Product revisions
Page 17 and 18: Functional Overview 2.1 PrimeCell S
Page 19 and 20: Functional Overview 2.2.1 AMBA APB
Page 21 and 22: Functional Overview 2.3 PrimeCell S
Page 23 and 24: Functional Overview The Serial Cloc
Page 25 and 26: Functional Overview SSPCLKOUT/ SSPC
Page 27 and 28: Functional Overview SSPCLKOUT/ SSPC
Page 29 and 30: Functional Overview However, in the
Page 31 and 32: Functional Overview Note The off-ch
Page 33 and 34: Functional Overview PL022 configure
Page 35: Functional Overview Table 2-1 shows
Page 39 and 40: Programmer’s Model 3.3 Register d
Page 41 and 42: Programmer’s Model Table 3-3 show
Page 43 and 44: Programmer’s Model Table 3-5 show
Page 45 and 46: Programmer’s Model Table 3-7 SSPI
Page 47 and 48: Programmer’s Model 15 2 1 0 Reser
Page 49 and 50: Programmer’s Model SSPPeriphID0 r
Page 51 and 52: Programmer’s Model 15 8 7 0 Reser
Page 53 and 54: Programmer’s Model SSPPCellID2 re
Page 55 and 56: Programmer’s Model 3.4 Interrupts
Page 57 and 58: Chapter 4 Programmer’s Model for
Page 59 and 60: Programmer’s Model for Test 4.2 S
Page 61 and 62: Programmer’s Model for Test 4.3.2
Page 63 and 64: Programmer’s Model for Test Table
Page 65 and 66: Programmer’s Model for Test conne
Page 67 and 68: Programmer’s Model for Test 4.5.2
Page 69 and 70: Programmer’s Model for Test 4.6 I
Page 71 and 72: Appendix A Signal Descriptions This
Page 73 and 74: Signal Descriptions A.2 On-chip sig
Page 75 and 76: Appendix B Revisions This appendix

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