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low-pass filter and UHF signal are high-pass filter, and then<br />
applied to the VHF and UHF power amplifier circuit separately.<br />
4-2-7 POWER AMPLIFIER CIRCUIT (PA UNIT)<br />
The power amplifier circuit amplifies the RF signals to the<br />
specified output power.<br />
(1) VHF power amplifier circuit<br />
The RF signal from the low-pass filter circuit is applied to the<br />
VHF power amplifier circuit (Q651, Q652) to obtain a stable<br />
100 W of RF output power. The amplified RF signal is<br />
applied to the antenna connector (CHASSIS; J1) via the<br />
power detector (D720, D721), transmit/receive switching<br />
relay (RL700) and low-pass filter (L723–L721, C728–C726,<br />
C728) circuits.<br />
(2) UHF power amplifier circuit<br />
The RF signal from the high-pass filter is applied to the<br />
UHF power amplifier circuit (Q151, Q152) to obtain a stable<br />
75 W of RF output power. The amplified RF signal is<br />
applied to the antenna connector (CHASSIS; J2) via the<br />
transmit/receive switching circuit (D182–D185), low-pass<br />
filter (L181, L180, C188–C184) and power detector (D180,<br />
D181) circuits.<br />
4-2-8 ALC CIRCUIT (PA AND MAIN UNITS)<br />
The ALC (Automatic Level Control) circuit protects the<br />
power amplifiers (PA unit; Q651, Q652 for VHF and Q151,<br />
Q152 for UHF) from a mismatched output load. Also, the<br />
ALC circuit controls the gain of the transmit IF amplifier in<br />
order for the transceiver to output even when the supplied<br />
voltage shifts, etc.<br />
The RF power level is detected at the power detector circuit<br />
(PA unit; D720–D721 for VHF, D180, D181 for UHF) to be<br />
converted into DC voltages. The detected voltage (VFOR for<br />
VHF or UFOR for UHF) is passed through the switching<br />
diode, and are then applied to the differential amplifier<br />
(MAIN unit; <strong>IC</strong>1601b) via the FOR line. A reference voltage<br />
(POCV) for <strong>IC</strong>1601b is controlled by the [RF PWR] control<br />
to output reference voltages. The output voltage is applied<br />
to the transmit IF amplifier circuit (MAIN unit; Q1) as an ALC<br />
signal to control the amplifier gain.<br />
When the VFOR/UFOR voltage increased, the output from<br />
the differential amplifier will be decrease to reduce the IF<br />
amplifier gain. This adjusts the RF output power until the<br />
VFOR/UFOR and POCV voltage are well balanced.<br />
4-3 PLL CIRCUITS<br />
<strong>IC</strong>-<strong>910H</strong> contains 2 PLL circuits and 1 local oscillator. The<br />
VHF and UHF PLL circuits adopt “Icom’s original I-loop PLL”<br />
to obtain very fast lock up times.<br />
4-3-1 VHF PLL CIRCUIT (PLL UNIT)<br />
The VHF PLL circuit generates the 1st LO frequency, and<br />
the signal is applied to the VHF 1st mixer circuit in the PA<br />
unit as the “A1LO” signal. The PLL circuit consists of a VCO,<br />
prescaler and DDS circuits.<br />
The signal generated at the VHF VCO circuit (Q191,<br />
D191–D194) is amplified at the buffer amplifiers (Q192,<br />
Q272), then applied to the prescaler circuit (<strong>IC</strong>271). The<br />
prescaler circuit divides the applied signal, and outputs it to<br />
the VHF DDS circuit (<strong>IC</strong>131) via the buffer amplifier (Q271).<br />
The VHF DDS circuit generates digital signals using the<br />
applied signals as a clock frequency. The phase detector<br />
section in <strong>IC</strong>131 compares its phase with the reference frequency<br />
that is generated at the reference oscillator (X512).<br />
<strong>IC</strong>131 outputs off-phase components as pulse signals via<br />
pins 51, 52.<br />
The output pulses are converted into DC voltage at the loop<br />
filter circuit (<strong>IC</strong>161a) and then applied to the VHF VCO circuit.<br />
The D/A converter (R101–R124), low-pass filter<br />
(L101–L103, C103–C110) and buffer amplifier (<strong>IC</strong>101) circuits<br />
are connected to the DDS output to convert the digital<br />
oscillated signals into smooth analog signals.<br />
4-3-2 UHF PLL CIRCUIT (PLL UNIT)<br />
The UHF PLL circuit generates the 1st LO frequency, and<br />
the signal is applied to the UHF 1st mixer circuit in the PA<br />
unit as the “B1LO” signal. The PLL circuit consists of a VCO,<br />
prescaler and DDS circuits.<br />
The signal generated at the UHF VCO circuit (Q391,<br />
D391–D394) is amplified at the buffer amplifiers (Q392,<br />
Q472), then applied to the prescaler circuit (<strong>IC</strong>471). The<br />
prescaler circuit divides the applied signal, and outputs it to<br />
the UHF DDS circuit (<strong>IC</strong>331) via the buffer amplifier (Q471).<br />
The D/A converter (R301–R324), low-pass filter<br />
(L301–L303, C103–C311) and buffer amplifier (<strong>IC</strong>301) circuits<br />
are connected to the DDS output to convert the digital<br />
oscillated signals into smooth analog signals.<br />
4-2-9 APC CIRCUIT (MAIN UNIT)<br />
The APC (Automatic Power Control) circuit protects the<br />
power amplifiers on the PA unit from excessive current.<br />
Current drain of power amplifiers is detected by voltage<br />
drops at a resistor (PA unit; R305) between VCC and PAHV<br />
lines. The original voltage (<strong>IC</strong>H) and dropped voltage (<strong>IC</strong>L)<br />
are applied to the APC differential amplifier (MAIN unit;<br />
<strong>IC</strong>1601d).<br />
The signal output from the differential amplifier reduces IF<br />
amplifier gain until these voltages are well-balanced.<br />
4-4 UX-910 (1200 MHz BAND UNIT)<br />
UX-910 is an optional 1200 MHz band unit for <strong>IC</strong>-<strong>910H</strong>. This<br />
unit covers 1240–1300 MHz frequency range.<br />
4-4-1 ANTENNA SWITCHING CIRCUIT (for RX)<br />
Received signals from the antenna connector (CHASSIS;<br />
J501) are applied to the transmit/receive switching circuit<br />
(RL51).<br />
The transmit/receive switching circuit leads receive signal to<br />
the RF circuit while receiving. However, the circuit leads the<br />
transmit signal from the RF power amplifier to the antenna<br />
connector while transmitting.<br />
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