DS2155 T1/E1/J1

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3. LIST OF TABLESTable 5-1 PIN DESCRIPTION SORTED BY PIN NUMBER.....................................................................26Table 6-1 REGISTER MAP SORTED BY ADDRESS................................................................................29Table 10-1 T1 ALARM CRITERIA .............................................................................................................49Table 11-1 E1 SYNC/RESYNC CRITERIA ................................................................................................51Table 11-2 E1 ALARM CRITERIA .............................................................................................................56Table 15-1 T1 LINE CODE VIOLATION COUNTING OPTIONS............................................................71Table 15-2 E1 LINE CODE VIOLATION COUNTING OPTIONS............................................................71Table 15-3 T1 PATH CODE VIOLATION COUNTING ARRANGEMENTS...........................................73Table 15-4 T1 FRAMES OUT OF SYNC COUNTING ARRANGEMENTS.............................................73Table 17-1 TIME SLOT NUMBERING SCHEMES ...................................................................................85Table 18-1 IDLE CODE ARRAY ADDRESS MAPPING...........................................................................94Table 20-1 ELASTIC STORE DELAY AFTER INITIALIZATION.........................................................106Table 24-1 HDLC CONTROLLER REGISTERS ......................................................................................127Table 25-1 TRANSFORMER SPECIFICATIONS.....................................................................................159Table 28-1 TRANSMIT ERROR INSERTION SETUP SEQUENCE .......................................................179Table 28-2 ERROR INSERTION EXAMPLES .........................................................................................181Table 34-1 INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE ............................................197Table 34-2 ID CODE STRUCTURE ..........................................................................................................198Table 34-3 DEVICE ID CODES.................................................................................................................198Table 34-4 BOUNDARY SCAN CONTROL BITS...................................................................................200DS215512 of 242
DS21553.1 DOCUMENT REVISION HISTORY1) Initial Preliminary Release, 0312012) Correct text on SR2, SR3, SR4 operation, 0426013) Correct status register operation details, 0504014) Remove references to TTL levels, 0507015) Remove reference to FMS pin; correct basic LIU connections diagram, 0518016) Add section on Clock Map, 0531017) Correct T1 pre-scale values LIC4 register; add jitter tolerance curve for E1 mode; correct sample codefor receiving an HDLC message; add capacitive test loads information, 0612018) Add E1 functional timing diagrams; improve block diagrams, 0625019) Add status register description to LIU section, 08140110) Add text on interrupt usage, 09050111) Change t DHW timing spec for muxed bus operation from 0ns to 5ns. Removed t DDR min value, 10220113 of 242
Page 1 and 2: DS2155T1/E1/J1 Single-Chip Transcei
Page 3 and 4: 3 of 242DS21551.1 FEATURE HIGHLIGHT
Page 5 and 6: 1.1.7 HDLC ControllersTwo independe
Page 7 and 8: 11.3 E1 INFORMATION REGISTERS .....
Page 9 and 10: 34.5 IDENTIFICATION REGISTER ......
Page 11: Figure 37-11 TRANSMIT SIDE TIMING..
Page 15 and 16: LINE INTERFACE UNIT Figure 4-2DS215
Page 17 and 18: BACKPLANE INTERFACE Figure 4-4DS215
Page 19 and 20: DS2155Signal Name:TSSYNCSignal Desc
Page 22 and 23: DS2155Signal Name:RPOSISignal Descr
Page 24 and 25: 5.6 JTAG Test Access Port PinsDS215
Page 26 and 27: 5.9 L and G Package PinoutThe DS215
Page 28 and 29: 5.10 10mm STBGA PackageDS215510mm S
Page 30 and 31: ADDRESS R/W REGISTER NAMEREGISTERAB
Page 32: ADDRESS R/W REGISTER NAMEREGISTERAB
Page 35: DS2155Register Name:PCDR1Register D
Page 40 and 41: DS21559. CLOCK MAPFigure 9-1 shows
Page 42 and 43: DS2155Register Name:T1RCR2Register
Page 44 and 45: DS2155Register Name:T1TCR2Register
Page 46 and 47: DS215510.2 T1 Transmit Transparency
Page 48 and 49: 10.4 T1 Information RegisterDS2155R
Page 50 and 51: DS215511. E1 FRAMER/FORMATTER CONTR
Page 52 and 53: DS2155Register Name:E1TCR1Register
Page 54 and 55: DS215511.2 Automatic Alarm Generati
Page 56 and 57: E1 ALARM CRITERIA Table 11-2DS2155A
Page 59 and 60: DS2155Register Name:IMR2Register De
Page 61 and 62: DS2155Register Name:IMR3Register De
Page 63 and 64:
DS2155Register Name:IMR4Register De
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DS2155Register Name: IOCR2Register
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DS2155Bit 3/Local Loopback (LLB). I
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DS2155Register Name:PCLR3Register D
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15.2 Path Code Violation Count Regi
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DS2155Register Name:FOSCR1Register
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16.2 Receive DS0 Monitor RegistersD
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DS215517.1.1 Processor-Based Receiv
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DS2155Register Name:Register Descri
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DS215517.2.1.1 T1 ModeIn T1 ESF fra
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DS2155Register Name:SSIE3Register D
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DS215517.2.4 Hardware-Based Transmi
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18.1 Idle Code Programming Examples
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DS2155Register Name:TCICE3Register
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DS215519. CHANNEL BLOCKING REGISTER
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DS2155Register Name:TCBR3Register D
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20.1 Receive SideSee the IOCR1 and
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DS215521. G.706 INTERMEDIATE CRC-4
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DS215523.3 Internal Register Scheme
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HDLC CONTROLLER REGISTERS Table 24-
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24.3 HDLC MappingDS215524.3.1 Recei
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24.3.2 TransmitThe HxTCS1-HxTCS4 re
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DS2155Register Name:SR6, SR7Registe
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24.3.5 HDLC FIFOSDS2155Register Nam
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DS215525. LINE INTERFACE UNIT (LIU)
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DS215525.2.2 Receive G.703 Section
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DS2155an accuracy of ±32ppm for T1
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E1 ModeDS2155L2 L1 L0 APPLICATION N
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DS2155Register Name:LIC2Register De
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DS2155Register Name:LIC4Register De
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DS2155Register Name:SR1Register Des
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25.8 Recommended CircuitsDS2155BASI
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25.9 Component SpecificationsDS2155
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JITTER TOLERANCE (T1 MODE) Figure 2
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OPTIONAL CRYSTAL CONNECTIONS Figure
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DS2155Register Name:TCD1Register De
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DS2155Register Name:RDNCD1Register
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DS2155Register Name:RSCD1Register D
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27.1 BERT Register DescriptionDS215
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DS215527.3 BERT Bit CounterOnce BER
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DS215528. PAYLOAD ERROR INSERTION F
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DS215528.1 Number Of Error Register
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DS215529. INTERLEAVED PCM BUS OPERA
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IBO EXAMPLE Figure 29-1DS2155RSYSCL
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DS2155Register Name:ESIBCR1Register
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DS2155Register Name:ESIB1Register D
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DS215532. FRACTIONAL T1/E1 SUPPORTT
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DS215534. JTAG-BOUNDARY-SCAN ARCHIT
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DS2155Select-IR-ScanAll test regist
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DS215534.1 Instruction RegisterThe
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DS215534.2 Test RegistersIEEE 1149.
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BIT PIN SYMBOL TYPE CONTROL BIT DES
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RECEIVE SIDE ESF TIMING Figure 35-2
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RECEIVE SIDE 1.544MHz BOUNDARY TIMI
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TRANSMIT SIDE D4 TIMING Figure 35-6
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TRANSMIT SIDE BOUNDARY TIMING (With
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DS2155TRANSMIT SIDE 2.048MHz BOUNDA
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RECEIVE SIDE BOUNDARY TIMING (With
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RECEIVE SIDE BOUNDARY TIMING, RSYSC
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RECEIVE IBO FRAME INTERLEAVE MODE T
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TRANSMIT SIDE TIMING Figure 35-18DS
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TRANSMIT SIDE BOUNDARY TIMING, TSYS
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TRANSMIT IBO CHANNEL INTERLEAVE MOD
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36. OPERATING PARAMETERSDS2155ABSOL
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37. AC TIMING PARAMETERS AND DIAGRA
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MOTOROLA BUS TIMING (BTS = 1 / MUX
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INTEL BUS READ TIMING (BTS = 0 / MU
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37.3 Receive Side AC Characteristic
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RECEIVE SIDE TIMING, ELASTIC STORE
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37.4 Transmit AC CharacteristicsDS2
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TRANSMIT SIDE TIMING, ELASTIC STORE
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38. MECHANICAL DESCRIPTIONSDS215538
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DS2155 T1/E1/J1

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