DS2155 T1/E1/J1

More documents

Recommendations

Info

5.6 JTAG Test Access Port PinsDS2155Signal Name:JTRSTSignal Description: IEEE 1149.1 Test ResetSignal Type:InputJTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low tohigh. This action will set the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRSTlow. JTRST is pulled HIGH internally via a 10k resistor operation.Signal Name:JTMSSignal Description: IEEE 1149.1 Test Mode SelectSignal Type:InputThis pin is sampled on the rising edge of JTCLK and is used to place the test-access port into the various defined IEEE 1149.1states. This pin has a 10k pullup resistor.Signal Name:JTCLKSignal Description: IEEE 1149.1 Test Clock SignalSignal Type:InputThis signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.Signal Name:JTDISignal Description: IEEE 1149.1 Test Data InputSignal Type:InputTest instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor.Signal Name:JTDOSignal Description: IEEE 1149.1 Test Data OutputSignal Type:OutputTest instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be leftunconnected.5.7 Line Interface PinsSignal Name:MCLKSignal Description: Master Clock InputSignal Type:InputA (50ppm) clock source. This clock is used internally for both clock/data recovery and for the jitter attenuator for both T1 andE1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock ratecan be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS2155 in T1-only operation a 1.544MHz (50ppm)clock source can be used.Signal Name:XTALDSignal Description: Quartz Crystal DriverSignal Type:OutputA quartz crystal of 2.048MHz (optional 1.544MHz in T1-only operation) can be applied across MCLK and XTALD instead ofa clock source at MCLK. Leave open-circuited if a clock source is applied at MCLK.Signal Name:8XCLKSignal Description: Eight Times ClockSignal Type:OutputAn 8x clock that is locked to the recovered network clock provided from the clock/data recovery block (if the jitter attenuatoris enabled on the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit side).24 of 242
DS2155Signal Name:LIUCSignal Description: Line Interface ConnectSignal Type:InputTie low to separate the line interface circuitry from the framer/formatter circuitry and activate theTPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. Tie high to connect the line interface circuitry to the framer/formattercircuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When LIUC is tied high, thePOSI/TNEGI/TCLKI/ RPOSI/RNEGI/RCLKI pins should be tied low.Signal Name:RTIP and RRINGSignal Description: Receive Tip and RingSignal Type:InputAnalog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the network. See Line Interface Unit fordetails.Signal Name:TTIP and TRINGSignal Description: Transmit Tip and RingSignal Type:OutputAnalog line driver outputs. These pins connect via a 1:2 step-up transformer to the network. See Line Interface Unit for details.5.8 Supply PinsSignal Name:DV DDSignal Description: Digital Positive SupplySignal Type:Supply3.3V ±5%. Should be tied to the RV DD and TV DD pins.Signal Name:RV DDSignal Description: Receive Analog Positive SupplySignal Type:Supply3.3V ±5%. Should be tied to the DV DD and TV DD pins.Signal Name:TV DDSignal Description: Transmit Analog Positive SupplySignal Type:Supply3.3V ±5% Should be tied to the RV DD and DV DD pins.Signal Name:DV SSSignal Description: Digital Signal GroundSignal Type:SupplyShould be tied to the RV SS and TV SS pins.Signal Name:RV SSSignal Description: Receive Analog Signal GroundSignal Type:Supply0.0V. Should be tied to DV SS and TV SS .Signal Name:TV SSSignal Description: Transmit Analog Signal GroundSignal Type:Supply0.0V. Should be tied to DV SS and RV SS .25 of 242
Page 1 and 2: DS2155T1/E1/J1 Single-Chip Transcei
Page 3 and 4: 3 of 242DS21551.1 FEATURE HIGHLIGHT
Page 5 and 6: 1.1.7 HDLC ControllersTwo independe
Page 7 and 8: 11.3 E1 INFORMATION REGISTERS .....
Page 9 and 10: 34.5 IDENTIFICATION REGISTER ......
Page 11 and 12: Figure 37-11 TRANSMIT SIDE TIMING..
Page 13 and 14: DS21553.1 DOCUMENT REVISION HISTORY
Page 15 and 16: LINE INTERFACE UNIT Figure 4-2DS215
Page 17 and 18: BACKPLANE INTERFACE Figure 4-4DS215
Page 19 and 20: DS2155Signal Name:TSSYNCSignal Desc
Page 22 and 23: DS2155Signal Name:RPOSISignal Descr
Page 26 and 27: 5.9 L and G Package PinoutThe DS215
Page 28 and 29: 5.10 10mm STBGA PackageDS215510mm S
Page 30 and 31: ADDRESS R/W REGISTER NAMEREGISTERAB
Page 32: ADDRESS R/W REGISTER NAMEREGISTERAB
Page 35: DS2155Register Name:PCDR1Register D
Page 40 and 41: DS21559. CLOCK MAPFigure 9-1 shows
Page 42 and 43: DS2155Register Name:T1RCR2Register
Page 44 and 45: DS2155Register Name:T1TCR2Register
Page 46 and 47: DS215510.2 T1 Transmit Transparency
Page 48 and 49: 10.4 T1 Information RegisterDS2155R
Page 50 and 51: DS215511. E1 FRAMER/FORMATTER CONTR
Page 52 and 53: DS2155Register Name:E1TCR1Register
Page 54 and 55: DS215511.2 Automatic Alarm Generati
Page 56 and 57: E1 ALARM CRITERIA Table 11-2DS2155A
Page 59 and 60: DS2155Register Name:IMR2Register De
Page 65 and 66: DS2155Register Name: IOCR2Register
Page 67 and 68: DS2155Bit 3/Local Loopback (LLB). I
Page 69: DS2155Register Name:PCLR3Register D
Page 73 and 74: 15.2 Path Code Violation Count Regi
Page 75 and 76:
DS2155Register Name:FOSCR1Register
Page 77 and 78:
16.2 Receive DS0 Monitor RegistersD
Page 79 and 80:
DS215517.1.1 Processor-Based Receiv
Page 81 and 82:
DS2155Register Name:Register Descri
Page 83 and 84:
Page 85 and 86:
DS215517.2.1.1 T1 ModeIn T1 ESF fra
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
DS2155Register Name:SSIE3Register D
Page 93 and 94:
DS215517.2.4 Hardware-Based Transmi
Page 95 and 96:
18.1 Idle Code Programming Examples
Page 97 and 98:
DS2155Register Name:TCICE3Register
Page 99 and 100:
DS215519. CHANNEL BLOCKING REGISTER
Page 101 and 102:
DS2155Register Name:TCBR3Register D
Page 103 and 104:
Page 105 and 106:
20.1 Receive SideSee the IOCR1 and
Page 107 and 108:
DS215521. G.706 INTERMEDIATE CRC-4
Page 109 and 110:
Page 111 and 112:
DS2155Register Name:IMR8Register De
Page 113 and 114:
Page 115 and 116:
DS215523.3 Internal Register Scheme
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
Page 123 and 124:
Page 125 and 126:
Page 127 and 128:
HDLC CONTROLLER REGISTERS Table 24-
Page 129 and 130:
Page 131 and 132:
24.3 HDLC MappingDS215524.3.1 Recei
Page 133 and 134:
24.3.2 TransmitThe HxTCS1-HxTCS4 re
Page 135 and 136:
DS2155Register Name:SR6, SR7Registe
Page 137 and 138:
Page 139 and 140:
24.3.5 HDLC FIFOSDS2155Register Nam
Page 141 and 142:
Page 143 and 144:
DS215525. LINE INTERFACE UNIT (LIU)
Page 145 and 146:
DS215525.2.2 Receive G.703 Section
Page 147 and 148:
DS2155an accuracy of ±32ppm for T1
Page 149 and 150:
E1 ModeDS2155L2 L1 L0 APPLICATION N
Page 151 and 152:
DS2155Register Name:LIC2Register De
Page 153 and 154:
DS2155Register Name:LIC4Register De
Page 155 and 156:
DS2155Register Name:SR1Register Des
Page 157 and 158:
25.8 Recommended CircuitsDS2155BASI
Page 159 and 160:
25.9 Component SpecificationsDS2155
Page 161 and 162:
JITTER TOLERANCE (T1 MODE) Figure 2
Page 163 and 164:
OPTIONAL CRYSTAL CONNECTIONS Figure
Page 165 and 166:
DS2155Register Name:TCD1Register De
Page 167 and 168:
DS2155Register Name:RDNCD1Register
Page 169 and 170:
DS2155Register Name:RSCD1Register D
Page 171 and 172:
27.1 BERT Register DescriptionDS215
Page 173 and 174:
Page 175 and 176:
DS2155Register Name:IMR9Register De
Page 177 and 178:
DS215527.3 BERT Bit CounterOnce BER
Page 179 and 180:
DS215528. PAYLOAD ERROR INSERTION F
Page 181 and 182:
DS215528.1 Number Of Error Register
Page 183 and 184:
DS215529. INTERLEAVED PCM BUS OPERA
Page 185 and 186:
IBO EXAMPLE Figure 29-1DS2155RSYSCL
Page 187 and 188:
DS2155Register Name:ESIBCR1Register
Page 189 and 190:
DS2155Register Name:ESIB1Register D
Page 191 and 192:
DS215532. FRACTIONAL T1/E1 SUPPORTT
Page 193 and 194:
DS215534. JTAG-BOUNDARY-SCAN ARCHIT
Page 195 and 196:
DS2155Select-IR-ScanAll test regist
Page 197 and 198:
DS215534.1 Instruction RegisterThe
Page 199 and 200:
DS215534.2 Test RegistersIEEE 1149.
Page 201 and 202:
BIT PIN SYMBOL TYPE CONTROL BIT DES
Page 203 and 204:
RECEIVE SIDE ESF TIMING Figure 35-2
Page 205 and 206:
RECEIVE SIDE 1.544MHz BOUNDARY TIMI
Page 207 and 208:
TRANSMIT SIDE D4 TIMING Figure 35-6
Page 209 and 210:
TRANSMIT SIDE BOUNDARY TIMING (With
Page 211 and 212:
DS2155TRANSMIT SIDE 2.048MHz BOUNDA
Page 213 and 214:
RECEIVE SIDE BOUNDARY TIMING (With
Page 215 and 216:
RECEIVE SIDE BOUNDARY TIMING, RSYSC
Page 217 and 218:
RECEIVE IBO FRAME INTERLEAVE MODE T
Page 219 and 220:
TRANSMIT SIDE TIMING Figure 35-18DS
Page 221 and 222:
TRANSMIT SIDE BOUNDARY TIMING, TSYS
Page 223 and 224:
TRANSMIT IBO CHANNEL INTERLEAVE MOD
Page 225 and 226:
36. OPERATING PARAMETERSDS2155ABSOL
Page 227 and 228:
37. AC TIMING PARAMETERS AND DIAGRA
Page 229 and 230:
MOTOROLA BUS TIMING (BTS = 1 / MUX
Page 231 and 232:
INTEL BUS READ TIMING (BTS = 0 / MU
Page 233 and 234:
37.3 Receive Side AC Characteristic
Page 235 and 236:
RECEIVE SIDE TIMING, ELASTIC STORE
Page 237 and 238:
37.4 Transmit AC CharacteristicsDS2
Page 239 and 240:
TRANSMIT SIDE TIMING, ELASTIC STORE
Page 241 and 242:
38. MECHANICAL DESCRIPTIONSDS215538
show all

DS2155 T1/E1/J1

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?