DS2155 T1/E1/J1

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DS2155Signal Name:RPOSISignal Description: Receive Positive Data InputSignal Type:InputSampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tiedtogether for a NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.Signal Name:RNEGISignal Description: Receive Negative Data InputSignal Type:InputSampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and RNEGI can be tiedtogether for a NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.Signal Name:RCLKISignal Description: Receive Clock InputSignal Type:InputClock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be internally connected toRCLKO by tying the LIUC pin high.5.3 Parallel Control Port PinsSignal Name:INT*Signal Description: InterruptSignal Type:OutputFlags host controller during events, alarms, and conditions defined in the status registers. Active-low open-drain output.Signal Name:TSTRSTSignal Description: 3-State Control and Device ResetSignal Type:InputA dual-function pin. A zero-to-one transition issues a hardware reset to the DS2155 register set. A reset clears all configurationregisters. Configuration register contents are set to zero. Leaving TSTRST high will 3-state all output and I/O pins (includingthe parallel control port). Set low for normal operation. Useful in-board level testing.Signal Name:MUXSignal Description: Bus OperationSignal Type:InputSet low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.Signal Name:AD0 to AD7Signal Description: Data Bus [D0 to D7] or Address/Data BusSignal Type:Input/OutputIn nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an8-bit, multiplexed address/data bus.Signal Name:A0 to A6Signal Description: Address BusSignal Type:InputIn nonmultiplexed bus operation (MUX = 0), it serves as the address bus. In multiplexed bus operation (MUX = 1), these pinsare not used and should be tied low.Signal Name:BTSSignal Description: Bus Type SelectSignal Type:InputStrap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the function of the RD*(DS*),ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the function listed in parenthesis ().22 of 242
DS2155Signal Name:RD*(DS*)Signal Description: Read Input-Data StrobeSignal Type:InputRD* and DS* are active-low signals. DS active HIGH when MUX = 0. See bus timing diagrams.Signal Name:CS*Signal Description: Chip SelectSignal Type:InputMust be low to read or write to the device. CS* is an active-low signal.Signal Name:ALE(AS)/A7Signal Description: Address Latch Enable(Address Strobe) or A7Signal Type:InputIn nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), itserves to demultiplex the bus on a positive-going edge.Signal Name:WR*(R/W*)Signal Description: Write Input(Read/Write)Signal Type:InputWR* is an active-low signal.5.4 Extended System Information BusSignal Name:ESIBS0Signal Description: Extended System Information Bus Select 0Signal Type:Input/OutputUsed to group two to eight DS2155s into a bus-sharing mode for alarm and status reporting. See Extended System InformationBus (ESIB) for more details.Signal Name:ESIBS1Signal Description: Extended System Information Bus Select 1Signal Type:Input/OutputUsed to group two to eight DS2155s into a bus-sharing mode for alarm and status reporting. See Extended System InformationBus (ESIB) for more details.Signal Name:ESIBRDSignal Description: Extended System Information Bus ReadSignal Type:Input/OutputUsed to group two to eight DS2155s into a bus-sharing mode for alarm and status reporting. See Extended System InformationBus (ESIB) for more details.5.5 User-Output Port PinsSignal Name:UOP0/1/2/3Signal Description: User Output PortSignal Type:OutputThese output port pins can be set low or high via the CCR4.0 to CCR4.3 control bits. The pins are forced low on power-up andafter any device reset.23 of 242
Page 1 and 2: DS2155T1/E1/J1 Single-Chip Transcei
Page 3 and 4: 3 of 242DS21551.1 FEATURE HIGHLIGHT
Page 5 and 6: 1.1.7 HDLC ControllersTwo independe
Page 7 and 8: 11.3 E1 INFORMATION REGISTERS .....
Page 9 and 10: 34.5 IDENTIFICATION REGISTER ......
Page 11 and 12: Figure 37-11 TRANSMIT SIDE TIMING..
Page 13 and 14: DS21553.1 DOCUMENT REVISION HISTORY
Page 15 and 16: LINE INTERFACE UNIT Figure 4-2DS215
Page 17 and 18: BACKPLANE INTERFACE Figure 4-4DS215
Page 19 and 20: DS2155Signal Name:TSSYNCSignal Desc
Page 24 and 25: 5.6 JTAG Test Access Port PinsDS215
Page 26 and 27: 5.9 L and G Package PinoutThe DS215
Page 28 and 29: 5.10 10mm STBGA PackageDS215510mm S
Page 30 and 31: ADDRESS R/W REGISTER NAMEREGISTERAB
Page 32: ADDRESS R/W REGISTER NAMEREGISTERAB
Page 35: DS2155Register Name:PCDR1Register D
Page 40 and 41: DS21559. CLOCK MAPFigure 9-1 shows
Page 42 and 43: DS2155Register Name:T1RCR2Register
Page 44 and 45: DS2155Register Name:T1TCR2Register
Page 46 and 47: DS215510.2 T1 Transmit Transparency
Page 48 and 49: 10.4 T1 Information RegisterDS2155R
Page 50 and 51: DS215511. E1 FRAMER/FORMATTER CONTR
Page 52 and 53: DS2155Register Name:E1TCR1Register
Page 54 and 55: DS215511.2 Automatic Alarm Generati
Page 56 and 57: E1 ALARM CRITERIA Table 11-2DS2155A
Page 59 and 60: DS2155Register Name:IMR2Register De
Page 65 and 66: DS2155Register Name: IOCR2Register
Page 67 and 68: DS2155Bit 3/Local Loopback (LLB). I
Page 69: DS2155Register Name:PCLR3Register D
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15.2 Path Code Violation Count Regi
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DS2155Register Name:FOSCR1Register
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16.2 Receive DS0 Monitor RegistersD
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DS215517.1.1 Processor-Based Receiv
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DS2155Register Name:Register Descri
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DS215517.2.1.1 T1 ModeIn T1 ESF fra
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DS2155Register Name:SSIE3Register D
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DS215517.2.4 Hardware-Based Transmi
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18.1 Idle Code Programming Examples
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DS2155Register Name:TCICE3Register
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DS215519. CHANNEL BLOCKING REGISTER
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DS2155Register Name:TCBR3Register D
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20.1 Receive SideSee the IOCR1 and
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DS215521. G.706 INTERMEDIATE CRC-4
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DS2155Register Name:IMR8Register De
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DS215523.3 Internal Register Scheme
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HDLC CONTROLLER REGISTERS Table 24-
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24.3 HDLC MappingDS215524.3.1 Recei
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24.3.2 TransmitThe HxTCS1-HxTCS4 re
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DS2155Register Name:SR6, SR7Registe
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24.3.5 HDLC FIFOSDS2155Register Nam
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DS215525. LINE INTERFACE UNIT (LIU)
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DS215525.2.2 Receive G.703 Section
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DS2155an accuracy of ±32ppm for T1
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E1 ModeDS2155L2 L1 L0 APPLICATION N
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DS2155Register Name:LIC2Register De
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DS2155Register Name:LIC4Register De
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DS2155Register Name:SR1Register Des
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25.8 Recommended CircuitsDS2155BASI
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25.9 Component SpecificationsDS2155
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JITTER TOLERANCE (T1 MODE) Figure 2
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OPTIONAL CRYSTAL CONNECTIONS Figure
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DS2155Register Name:TCD1Register De
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DS2155Register Name:RDNCD1Register
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DS2155Register Name:RSCD1Register D
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27.1 BERT Register DescriptionDS215
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DS2155Register Name:IMR9Register De
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DS215527.3 BERT Bit CounterOnce BER
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DS215528. PAYLOAD ERROR INSERTION F
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DS215528.1 Number Of Error Register
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DS215529. INTERLEAVED PCM BUS OPERA
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IBO EXAMPLE Figure 29-1DS2155RSYSCL
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DS2155Register Name:ESIBCR1Register
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DS2155Register Name:ESIB1Register D
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DS215532. FRACTIONAL T1/E1 SUPPORTT
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DS215534. JTAG-BOUNDARY-SCAN ARCHIT
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DS2155Select-IR-ScanAll test regist
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DS215534.1 Instruction RegisterThe
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DS215534.2 Test RegistersIEEE 1149.
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BIT PIN SYMBOL TYPE CONTROL BIT DES
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RECEIVE SIDE ESF TIMING Figure 35-2
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RECEIVE SIDE 1.544MHz BOUNDARY TIMI
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TRANSMIT SIDE D4 TIMING Figure 35-6
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TRANSMIT SIDE BOUNDARY TIMING (With
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DS2155TRANSMIT SIDE 2.048MHz BOUNDA
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RECEIVE SIDE BOUNDARY TIMING (With
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RECEIVE SIDE BOUNDARY TIMING, RSYSC
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RECEIVE IBO FRAME INTERLEAVE MODE T
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TRANSMIT SIDE TIMING Figure 35-18DS
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TRANSMIT SIDE BOUNDARY TIMING, TSYS
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TRANSMIT IBO CHANNEL INTERLEAVE MOD
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36. OPERATING PARAMETERSDS2155ABSOL
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37. AC TIMING PARAMETERS AND DIAGRA
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MOTOROLA BUS TIMING (BTS = 1 / MUX
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INTEL BUS READ TIMING (BTS = 0 / MU
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37.3 Receive Side AC Characteristic
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RECEIVE SIDE TIMING, ELASTIC STORE
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37.4 Transmit AC CharacteristicsDS2
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TRANSMIT SIDE TIMING, ELASTIC STORE
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38. MECHANICAL DESCRIPTIONSDS215538
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DS2155 T1/E1/J1

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