DS2155 T1/E1/J1

24.2.1 FIFO Control ......................................................................................................................13024.3 HDLC MAPPING..........................................................................................................................13124.3.1 Receive.................................................................................................................................13124.3.2 Transmit...............................................................................................................................13324.3.3 FIFO Information................................................................................................................13824.3.4 Receive Packet Bytes Available...........................................................................................13824.3.5 HDLC FIFOs.......................................................................................................................14024.4 RECEIVE HDLC CODE EXAMPLE.................................................................................................14024.5 LEGACY FDL SUPPORT (T1 MODE).............................................................................................14024.5.1 Receive Section....................................................................................................................14224.5.2 Transmit Section..................................................................................................................14224.6 D4/SLC–96 OPERATION..............................................................................................................14225. LINE INTERFACE UNIT (LIU) .................................................................................................14325.1 LIU OPERATION ..........................................................................................................................14425.2 LIU RECEIVER.............................................................................................................................14425.2.1 Receive Level Indicator .......................................................................................................14425.2.2 Receive G.703 Section 10 Synchronization Signal ..............................................................14525.2.3 Monitor Mode......................................................................................................................14525.3 LIU TRANSMITTER ......................................................................................................................14625.3.1 Transmit Short Circuit Detector / Limiter ...........................................................................14625.3.2 Transmit Open Circuit Detector..........................................................................................14625.3.3 Transmit BPV Error Insertion.............................................................................................14625.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode) ..........................................14625.4 MCLK PRESCALER......................................................................................................................14625.5 JITTER ATTENUATOR ...................................................................................................................14725.6 CMI (CODE MARK INVERSION) OPTION......................................................................................14725.7 LIU CONTROL REGISTERS ...........................................................................................................14825.8 RECOMMENDED CIRCUITS ...........................................................................................................15725.9 COMPONENT SPECIFICATIONS......................................................................................................15926. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION ............163DS215527. BERT FUNCTION........................................................................................................................17027.1 BERT REGISTER DESCRIPTION....................................................................................................17127.2 BERT REPETITIVE PATTERN SET.................................................................................................17627.3 BERT BIT COUNTER ...................................................................................................................17727.4 BERT ERROR COUNTER ..............................................................................................................17828. PAYLOAD ERROR INSERTION FUNCTION ........................................................................17928.1 NUMBER OF ERRORS REGISTERS .................................................................................................18128.1.1 Number Of Errors Left Register ..........................................................................................18229. INTERLEAVED PCM BUS OPERATION................................................................................18329.1 CHANNEL INTERLEAVE MODE ....................................................................................................18329.2 FRAME INTERLEAVE MODE.........................................................................................................18530. EXTENDED SYSTEM INFORMATION BUS (ESIB) .............................................................18631. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER...............................................19032. FRACTIONAL T1/E1 SUPPORT ...............................................................................................19133. USER-PROGRAMMABLE OUTPUT PINS..............................................................................19234. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................19334.1 INSTRUCTION REGISTER...............................................................................................................19734.2 TEST REGISTERS ..........................................................................................................................19834.3 BOUNDARY SCAN REGISTER........................................................................................................19934.4 BYPASS REGISTER........................................................................................................................1998 of 242