DS2155 T1/E1/J1

TABLE OF CONTENTS1. DESCRIPTION .....................................................................................................................................21.1 FEATURE HIGHLIGHTS .....................................................................................................................31.1.1 General....................................................................................................................................31.1.2 Line Interface ..........................................................................................................................31.1.3 Clock Synthesizer.....................................................................................................................31.1.4 Jitter Attenuator.......................................................................................................................41.1.5 Framer/Formatter ...................................................................................................................41.1.6 System Interface.......................................................................................................................41.1.7 HDLC Controllers ...................................................................................................................51.1.8 Test and Diagnostics ...............................................................................................................51.1.9 Extended System Information Bus ...........................................................................................51.1.10 User-Programmable Output Pins............................................................................................51.1.11 Control Port ............................................................................................................................52. LIST OF FIGURES.............................................................................................................................10DS21553. LIST OF TABLES...............................................................................................................................123.1 DOCUMENT REVISION HISTORY.....................................................................................................134. BLOCK DIAGRAM............................................................................................................................145. PIN FUNCTION DESCRIPTION .....................................................................................................185.1 TRANSMIT SIDE PINS .....................................................................................................................185.2 RECEIVE SIDE PINS ........................................................................................................................205.3 PARALLEL CONTROL PORT PINS ....................................................................................................225.4 EXTENDED SYSTEM INFORMATION BUS.........................................................................................235.5 USER OUTPUT PORT PINS...............................................................................................................235.6 JTAG TEST ACCESS PORT PINS .....................................................................................................245.7 LINE INTERFACE PINS ....................................................................................................................245.8 SUPPLY PINS ..................................................................................................................................255.9 L AND G PACKAGE PINOUT ...........................................................................................................265.10 10MM STBGA PACKAGE...............................................................................................................286. PARALLEL PORT .............................................................................................................................296.1 REGISTER MAP...............................................................................................................................297. SPECIAL PER-CHANNEL REGISTER OPERATION.................................................................348. PROGRAMMING MODEL...............................................................................................................368.1 POWER-UP SEQUENCE ...................................................................................................................378.1.1 Master Mode Register ...........................................................................................................378.2 INTERRUPT HANDLING...................................................................................................................388.3 STATUS REGISTERS........................................................................................................................388.4 INFORMATION REGISTERS..............................................................................................................398.5 INTERRUPT INFORMATION REGISTERS ...........................................................................................399. CLOCK MAP ......................................................................................................................................4010. T1 FRAMER/FORMATTER CONTROL REGISTERS ............................................................4110.1 T1 CONTROL REGISTERS ...............................................................................................................4110.2 T1 TRANSMIT TRANSPARENCY......................................................................................................4610.3 T1 RECEIVE SIDE DIGITAL MILLIWATT CODE GENERATION..........................................................4610.4 T1 INFORMATION REGISTER ..........................................................................................................4811. E1 FRAMER/FORMATTER CONTROL REGISTERS ............................................................5011.1 E1 CONTROL REGISTERS ...............................................................................................................5011.2 AUTOMATIC ALARM GENERATION ................................................................................................546 of 242