EUROPRACTICE IC Service MPW offering from imec anno 2010

EUROPRACTICE IC ServiceMPW offering from imec anno 2010Paul Malisseimec - BelgiumEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 1

Outline TSMC technology offering and access UMC technology offering and access On Semiconductor technology offering and access Mini@sic MEMS ConclusionEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 2

Europractice MPW TSMC offeringOverviewTECHNOLOGY OVERVIEWTECHNOLOGY NODE PROCESS APPLICATION CORE VOLTAGE I/O VOLTAGE65nm Logic / MS / RF LP 1.2V 2.5V90nm Logic / MS / RF GP / LP 1.0V / 1.2V 1.8V / 2.5V / 3.3V0.13µm Logic / MS / RF GP 12V 1.2V 25V 2.5V / 3.3V 33V0.18µm Logic / MS / RF GP 1.8V 3.3V0.25µm Logic / MS / RF GP 2.5V 3.3V / 5V(*) GP : General PurposeLP : Low PowerMS : Mixed-SignalRF : Radio-FrequencyEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 3

Europractice MPW TSMC offeringOverview65nmTECHNOLOGY NODE65nm MS/RF LP 1.2V/2.5V90nmTECHNOLOGY NODE90nm Logic GP 1.0V/1.8V90nm Logic GP 1.0V/2.5V90nm Logic GP 1.0V/3.3V90nm Logic GP 1.0V/1.8/3.3V90nm Logic LP 1.2V/2.5V90nm Logic LP 1.2V/3.3V90nm MS/RF GP 1.0V/2.5V90nm MS/RF GP 1.0V/3.3V90nm MS/RF GP 1.0V/1.8V/3.3V90nm MS/RF LP 1.2V/2.5V90nm MS/RF LP 1.2V/3.3V0.13µmTECHNOLOGY NODE0.13µm Logic GP 1.2V/2.5V0.13µm Logic GP 1.2V/3.3V0.13µm MS/RF GP 1.2V/2.5V0.13µm MS/RF GP 1.2V/3.3V0.18µmTECHNOLOGY NODE0.18µm Logic GP 1.8V/3.3V0.18µm MS/RF GP 1.8V/3.3V0.25µmTECHNOLOGY NODE0.25µm Logic GP 2.5V/3.3V0.25µm Logic GP 2.5V/5V0.25µm MS/RF GP 2.5V/3.3V0.25µm MS/RF GP 2.5V/5VEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 4

TSMC 65nm MS/RF LP 1.2V/2.5VTECHNOLOGY OVERVIEWTechnologyMS/RFGeometry65 nmDevice ApplicationLow PowerCore Voltage (V) 1.2VI/O Voltage (V) 2.5VBEOL DielectricLow-KBEOL MetalCuPoly Layers 1# of Metal Layers (Min/Max) 4/9PROCESS FEATURESWell FormationRetrogradeOn P-substrateSubstrate resistivityof 8-12 ohm/cmIsolationSTIGt Gate Mt Materials il N+/P+ poly gateSilicide MaterialNi-silicidedGate Dielectric tox N / P (core)26 A / 28 AGate Dielectric tox N / P (I/O)56 A / 59 ADefault # of MasksMORE FEATURES36 ( when 9 Metal)# of Optional Masks 18Made in FabFab12 (12-inch), Fab14 (12-inch)Gate Density(based on TSMC’s Standard Cell Library)854 Kgates/mm2Available PDK for :Cadence CDBA / OA / MentorMS / RF PROCESS MODULECore Transistor Vt High-Vt, Std-Vt, Low-VtMIMYMOMYInductorYHi ResistorN/AVaractorYTriple WellYEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 5

TSMC 90nm MS/RF GP 1.0V/2.5VTECHNOLOGY OVERVIEWTechnologyMS/RFGeometry90 nmDevice ApplicationGeneral PurposeCore Voltage (V) 1.0VI/O Voltage (V) 2.5VBEOL DielectricLow-KBEOL MetalCuPoly Layers 1# of Metal Layers (Min/Max) 3/9MORE FEATURESDefault # of Masks36 ( When 9 Metal)# of Optional Masks 11Made in FabFab12 (12-inch), Fab14 (12-inch)Gate Density (based on TSMC’sStandard Cell Library)436 Kgates/mm2Available PDK for :Cadence CDBA / MentorWell FormationIsolationGate MaterialsSilicide MaterialGate Dielectric toxN / P (core)Gate Dielectric toxN / P (I/O)PROCESS FEATURESRetrograde WellSTISilicideCobalt-silicideCore Transistor VtMIMMOMInductorHi ResistorVaractorTriple Well23.3 A / 25 A55.4 A / 58.2 AMS / RF PROCESS MODULEHigh-Vt, Std-Vt, Low-VtYYYN/AYYEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 6

TSMC 0.13µm MS/RF GP 1.2V/3.3VTECHNOLOGY OVERVIEWTechnologyMS/RFGeometry 0.13 µmDevice ApplicationGeneral PurposeCore Voltage (V) 1.2VI/O Voltage (V) 3.3VBEOL DielectricFSG (K=3.6)BEOL MetalCuPoly Layers 1# of Metal Layers (Min/Max) 3/8MORE FEATURESDefault # of Masks33 ( When 8 Metal)# of Optional Masks 15Made in FabGate Density (based on TSMC’sStandard Cell Library)Available PDK for :Fab6 (8-inch), Fab12 (12-inch)219 Kgates/mm2Cadence CDBA / OAPROCESS FEATURESWell FormationSSRIsolationSTIGate MaterialsSilicideSilicide MaterialCobalt-silicideGt Gate Dil Dielectric ti tox (core)20 AGate Dielectric tox (I/O)70 AMS / RF PROCESS MODULECore Transistor VtHigh-Vt, Std-Vt, Low-Vt, NativeMIMYMOMYInductorYHi ResistorYVaractorYTriple WellYEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 7

TSMC 0.18µm MS/RF GP 1.8V/3.3VTECHNOLOGY OVERVIEWTechnologyMS/RFGeometry 0.18 µmDevice ApplicationGeneral PurposeCore Voltage (V) 1.8VI/O Voltage (V) 3.3VBEOL DielectricFSG (K=3.6)BEOL MetalAlPoly Layers 1# of Metal Layers (Min/Max) 3/6MORE FEATURESDefault # of Masks 26# of Optional Masks 9Made in FabFab3, Fab8, Fab11, SSMC(All 8-inch)Available PDK for :Cadence CDBAWell FormationPROCESS FEATURESSSRIsolationSTIGate MaterialsSilicideSilicide MaterialCobalt-silicideGt Gate Dil Dielectric ti tox (core)32 AGate Dielectric tox (I/O)70 ACore Transistor VtMIMMOMInductorHi ResistorVaractorTriple WellMS / RF PROCESS MODULEHigh-Vt, Std-Vt, Low-Vt, NativeYYYY (1050 Ω/□)YYEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 8

TSMC 0.25µm MS/RF GP 2.5V/5VTECHNOLOGY OVERVIEWTechnologyMS/RFGeometry 0.25 µmDevice ApplicationGeneral PurposeCore Voltage (V) 2.5VI/O Voltage (V)5VBEOL DielectricOxide IMDBEOL MetalAlPoly Layers 1# of Metal Layers (Min/Max) 3/5MORE FEATURESDefault # of Masks 26# of Optional Masks 7Made in FabGate Density (based on TSMC’sStandard Cell Library)Available PDK for :Fab3, Fab8, Fab10 (All 8-inch)219 Kgates/mm2Cadence CDBAPROCESS FEATURESWell FormationRetrograde WellIsolationSTIGate MaterialsSilicideSilicide MaterialTi-silicideGt Gate Dil Dielectric ti tox (core)50 AGate Dielectric tox (I/O)120 AMS / RF PROCESS MODULECore Transistor VtHigh-Vt, Std-Vt, Low-Vt, NativeMIMYMOMYInductorYHi ResistorY (400 Ω/□)VaractorYTriple WellY (DNW Optional)Europractice Service – Info Meeting – DATE2010 - 8 March 2010 - 9

TSMC Library offering by EuropracticeSummaryLIBRARIES OVERVIEWNODE TYPES OPTIONS65nm Std Cells, Dig/Ana I/Os, Bond Pad Std/Low/HighVt, Coarse-grain, Header Cells, Multi-Vdd, Flip-Flop Retention...90nm Std Cells, Dig/Ana I/Os, Bond Pad Std/Ultra-Low/Low/HighVt, Coarse-grain, Tap-less Cells, Multi-Vdd, Underdrive...0.13µm Std Cells, Digital I/Os, Bond Pad Overdrive tolerant, Linear/Staggered I/Os, Linear/Staggered Bond Pads...0.18µm Std Cells, Digital I/Os, Bond Pad Overdrive tolerant, Linear I/Os, SAGE-XTM Std Cells...0.25µm Std Cells, Digital I/Os Overdrive tolerant, Linear/Staggered I/Os, SAGE-XTM Std Cells...(*) Std : StandardDig : DigitalAna : AnalogLP : Low Power(*) 0.13um, 0.18um, 0.25um• standardcells = ARM/Artisan• IO-cells = TSMC65nm, 90nm: Standarcell + IO-cells = TSMC librariesEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 10

TSMC Library offering by EuropracticeExamples65nm TECHNOLOGY NODEIP NAME TYPE DESCRIPTIONTCBN65LPCGHVT Standard cell LP process (1P9M, core 1.2V), 9-Track, Coarse-grain MTCMOS, High-Vt90nm TECHNOLOGY NODEIP NAME TYPE DESCRIPTIONTCBN90LPHDBWPHVT Standard d cell LP, Tap-less (tied to VDD/VSS), High Vt, 7-track, Characterized for 1.0V 10V0.13µm TECHNOLOGY NODEIP NAME TYPE DESCRIPTIONTPZ013G3 Standard I/O 1.2V/3.3V, 5V tolerant, staggered universal standard I/O0.18µm TECHNOLOGY NODEIP NAME TYPE DESCRIPTIONTPZ018NV Standard I/O 1.8V/3.3V, 5V Tolerant, Linear Universal Standard I/O0.25µm TECHNOLOGY NODEIP NAME TYPE DESCRIPTIONSTDCEL_CL025G Standard Cell 2.5-Volt SAGE-XTM Standard Cell Library 2004q2v1Europractice Service – Info Meeting – DATE2010 - 8 March 2010 - 11

Easy TSMC Access for Academic &Research institutes ? 0.25u, 0.18u, 130nm, 90nm Signing the imec-TSMC customer agreement for these technologies 65nm Signing the imec-TSMC customer agreement for TSMC 65nmtechnology www.europractice-ic.com/nda_TSMC.phppp www.europractice-online.beEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 12

Process Design Kit Installation(TSMC example)Download a ZIP fileFrom a linux/unixunix system, unzip the file in achosen directoryEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 13

Process Design Kit InstallationUncompress/untarthe tar fileEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 14

Process Design Kit InstallationEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 15

Process Design Kit Installation pdkInstall.plRun pdkInstall.pl to select your technology settingEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 16

Process Design Kit InstallationConfirm technology settingStart PDK using Cadence commandEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 17

Outline TSMC technology offering and access UMC technology offering and access On Semi technology offering and access Mini@sic MEMS ConclusionEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 18

Europractice MPW UMC offeringOverviewTECHNOLOGYNODEUMC THROUGH EUROPRACTICE MPW TECHNOLOGY OVERVIEWPROCESSCOREDEVICESCORE VOLTAGEI/O VOLTAGE90nm Logic / MM - RF SP / LL SP 1.0V(1.2V*) / LL 1.2V 18V 1.8V / 25V 2.5V / 3.3V 33V0.13µm Logic / MM - RF SP / LL / HS 1.2V 3.3V0.18µm G2 / MM – RF / LL / CIS SP 1.8V 3.3V*G2 : LogicMM : Mixed ModeRF : Radio FrequencyCIS : CMOS Image SensorsSP : Standard PerformanceLL : Low LeakageHS : High Speed** Overdrive feasibilityEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 19

Europractice MPW UMC offeringOverview90nm TECHNOLOGY NODE (Logic and MM/RF)1.8V or 2.5V or 3.3V I/O90nm SP_RVt 1.0V (1.2V)90nm SP_LVt 1.0V (1.2V) (RF model available)90nm SP_HVt 1.0V (1.2V)90nm LL_RVt 1.2V90nm LL_LVt 1.2V (RF model available)90nm LL_HVt 1.2V0.13µm TECHNOLOGY NODE (Logic and MMRF)3.3V I/O0.13µm HS 1.2V0.13µm SP 1.2V0.13µm LL 1.2V0.13µm HS+LL 1.2V0.13µm HS+SP 1.2V0.13µm SP+LL 1.2V0.18µm TECHNOLOGY NODE3.3V I/O0.18µm Logic G2 1.8V0.18µm Logic Low Leakage 1.8V0.18µm Mixed-Mode/RF Mode/RF 1.8VRVt : Regular Threshold Voltage deviceLVt : Low Threshold Voltage deviceHVt : High Threshold Voltage deviceEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 20

UMC 90nm MM-RF SP/LL 1.2V/2.5VTECHNOLOGY OVERVIEWPROCESS FEATURESTechnology Mixed Mode RFWell FormationRetrograde Twin wellGeometry90 nmOn P-substrateDeviceSP and LLSubstrate resistivityof 15-25 ohm-cmCore Voltage (V)1.0 /1.2VIsolationSTII/O Voltage (V) 2.5VGate MaterialsN+/P+ poly gateBEOL DielectricLow-K / FSGGate Dielectric tox N / P (core)22 ABEOL MetalCuGate Dielectric tox N / P (I/O)52 APoly Layers 1# of Metal Layers (Max) 9OPTIONSAti ActiveNative Vt (thin and thick Ox)SPECIFICATIONSBipolarPassiveTotal # of Masks 43MOS VaractorMade in FabFAB 12 inch waferHipo ResistorGate Density (based on FaradayDiodes400 Kgates/mm2estimation)MIMMOMPerformance (Ft/10)14GHzNCAP (thin and thick Ox)Available EDA tools forCadence / Synopsis / MentorInductorsRedistributionAluminiumTriple WellEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 21

UMC 130nm MM-RF HS/SP/LL12V/33V 1.2V/3.3VTECHNOLOGY OVERVIEWPROCESS FEATURESTechnology Mixed Mode RFWell FormationRetrograde Twin wellGeometry130 nmOn P-substrateDevice ApplicationHS, SP and LLSubstrate resistivityof 15-25 ohm-cmCore Voltage (V) 1.2VIsolationSTII/O Voltage (V) 3.3VGate MaterialsN+/P+ poly gateBEOL DielectricFSGGate Dielectric tox N / P (core)22 ABEOL MetalCuGate Dielectric tox N / P (I/O)65 APoly Layers 1# of Metal Layers (Max) 8OPTIONSAti ActiveNative Vt (thin and thick Ox)SPECIFICATIONSBipolarPassiveTotal # of Masks (all options) 45MOS VaractorMade in FabFAB 8 / 12 inch wafersHipo ResistorGate Density (based on UMCDiodes220 Kgates/mm2estimation)MIMMOMPerformance (Ft/10)11GHzNCAP (thin and thick Ox)Available EDA tools for Cadence / Synopsis/ ADS / MentorInductorsRedistributionAluminiumTriple WellEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 22

UMC 180nm MM-RF 1.8V/3.3VTECHNOLOGY OVERVIEWTechnology Mixed Mode RFGeometry180 nmDevice ApplicationStandardCore Voltage (V) 1.8VI/O Voltage (V) 3.3VBEOL DielectricFSGBEOL MetalAlPoly Layers 1# of Metal Layers (Max) 6SPECIFICATIONSTotal # of Masks (all options) 35Made in FabFAB 8 inch waferGate Density (based on UMCestimation)100 Kgates/mm2Performance (Ft/10)5 GHzCadence / Synopsis/ ADS /Available EDA tools forMentorPROCESS FEATURESWell FormationRetrograde Twin wellOn P-substrateSubstrate resistivityof 15-25 ohm-cmIsolationSTIGate MaterialsN+/P+ poly gateGate Dielectric tox N / P (core)33 AGate Dielectric tox N / P (I/O)65 AOPTIONSActiveNative Vt (thin and thick Ox)BipolarPassiveMOS VaractorHipo ResistorDiodesMIMInductorsTriple WellEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 23

FARADAY IP Libraries for UMCSummaryFARADAY LIBRARIES OVERVIEWNODE TYPES OPTIONS90nm Std Cells, Dig/Ana I/Os, Memories, PLL SP Low-K (RVt, HVt, LVt) / LL Low-K (RVt, HVt, LVt)0.13µm Std Cells, Dig/Ana I/Os, Memories, PLL SP / LL / HS / Fusion018 0.18µm Std Cells, Dig/Ana I/Os, Memories, PLL CIS / G2 / LL / MM-RF(*) Std : StandardDig : DigitalAna : AnalogEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 24

FARADAY IP Libraries for UMCExamples90nm TECHNOLOGY NODELIB NAME TYPE DESCRIPTIONFSD0A_B_GENERIC_CORE Standard d cell 10V 1.0V Core Cells SP Low-K RVt0.13µm TECHNOLOGY NODELIB NAME TYPE DESCRIPTIONFSC0G_D_50VT_GENERIC_IO _ _ _ Standard I/O SP True 3.3V programmable I/O 3.3V programmable I/O with 5V tolerance0.18µm TECHNOLOGY NODEIP NAME TYPE DESCRIPTIONFSA0L_A_SH 1P SRAM LL Synchronous, high density single port RAM(*) Std : StandardDig : DigitalAna : AnalogLP : Low PowerEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 25

Special library for UMC: DARE Imec has developed a radiation hard library radiation hard by design techniques Available in UMC 180nm technology Available upon request and commercial agreementEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 26

Easy UMC Access for Academic &Research institutes ? 0.25u, 0.18u, 130nm, 90nm Signing the imec-UMC NDA• Only one NDA for all technologies www.europractice-ic.com/nda ic.com/nda_UMC.php www.europractice-online.beEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 27

Outline TSMC technology offering and access UMC technology offering and access On Semiconductor technology offering and access Mini@sic MEMS ConclusionEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 28

On Semiconductor CMOS 0.7μmProcess Name C07-D C07-A I2T30 I2T30E I2T100Geometry 0.7um 0.7um 0.7um 0.7um 0.7umSubstrate TypePepi on POperating Voltage (V) 3.3 / 5 3.3 / 5 30 30 100IsolationLOCOSPoly Layers 1 1 1 1 2Poly Pitch (um) 1.5Metal Layers (Min) 2Metal Layers (Max) 3N/PMOS Sat Current (uA/um) 358 / 176Poly resistors (kΩ/sq) N/A 2 2 2 2Precision Cap Poly/Poly (fF/um2) N/A N/A N/A N/A 0.36Precision Cap Poly/Diffusion (fF/um2) N/A 0.75 0.75 0.75 0.75Precision Cap MIMC (fF/um2)N/AEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 29

On Semiconductor CMOS 0.5μmProcess Name C05M C05 F/NRoute C05-D C05-AGeometry 0.5um 0.5um 0.6umSubstrate Type Pepi on P Pepi on PMetal Layers (Min) 3 3Metal Layers (Max) 3 3Operating Voltage (V) 3.3 / 5 2.5 / 3.3 / 5EEPROM N/A YN/PMOS Sat Current (uA/um) 381 / 166 510 / 290Poly res (kΩ/sq) N/A 1 1Precision Cap Poly/Poly (fF/um2) N/A 1.1 0.9Precision Cap Poly/Diffusion (fF/um2) N/A N/APrecision Cap MIMC (fF/um2) N/A N/ANumber of Core cells 276 332Gate density (NAND2 equiv.) (kgates/mm2) 5 5Logic Delay of NAND2 (ps) 190 100NAND2 Area (um2) 165 160Powerdissipation (NAND2) (uW/MHz) 0.6 0.16 / 0.28 / 0.63I/O cells 155 padgenEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 30

Om Semiconductor CMOS 0.35μmProcess Name C035M C035URouteC035- C035- C035-D A DC035-A I3T25 I3T50 I3T80Geometry 0.35um 0.35um 0.35um 0.35um 0.35um 0.35um 0.35umSubstrate Type Pepi on P Nepi on PIsolation LOCOS LOCOS DTI LOCOSMetal Layers (Max) 5 5Operating Voltage (V) 3.3 3.3 20 40 70HV transistors (V) N/A N/A N/A 25 50 80N/PMOS Saturation Current(uA/um)530 / 250 530 / 250Poly resistors (kΩ/sq) N/A 1 N/A 1 1Precision Cap Poly/Poly (fF/um2) N/A 1.1 N/APrecision Cap Poly/Diffusion(fF/um2)N/APrecision Cap MIMC (fF/um2) N/A N/A 1.5 1.5Bipolars (vertical) Y YN/AEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 31

On Semiconductor Design kit overviewProcess Name Design kit Linux Solaris WindowsC0.7M-A/D ADS Cadence 5.0.32 Cadence 5.0.32 Tanner L-EDITv8I2T30(E) ADS Cadence 5.0.32 Cadence 5.0.32I2T100 ADS - UDS ADS: Cadence 5.0.32 ADS: Cadence 5.0.32UDS: Cadence 5.1.41 UDS: Cadence 5.1.41C05M-A/D ADS Cadence 5.0.32 Cadence 5.0.32 Tanner L-EDITv10C5F/N UDS UDS: Cadence 5.1.41 UDS: Cadence 5.1.41 Tanner L-EDITv10C035M-A/D ADS Cadence 5.0.32 Cadence 5.0.32 Tanner L-EDITv10C035U-A/D & I3T25 UDS UDS: Cadence 5.1.41 UDS: Cadence 5.1.41I3T50 UDS UDS: Cadence 5.1.41 UDS: Cadence 5.1.41I3T80 UDS UDS: Cadence 5.1.41 UDS: Cadence 5.1.41Europractice Service – Info Meeting – DATE2010 - 8 March 2010 - 32

Easy On Semi Access for Academic &Research institutes ? 0.7u, 0.5u, 0.35u CMOS and HV technologies Signing the Design Kit License Agreement per Technology www.europractice-ic.com/nda_AMIS.php www.europractice-online.be CD-ROMEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 33

Outline TSMC technology offering and access UMC technology offering and access On Semiconductor technology offering and access Mini@sic MEMS ConclusionEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 34

How can we further lower the cost andoffer advanced technology ? Mini-asic principle and considerations Europe mainly Mixed Signal/RF oriented• Small die size OK for MSRFCMOS design Reducing the minimum area to be used Dividing foundry offered areas into smaller areas Use EC subsidy stimulating advanced technology Need a common technology platform to consolidate different designs• Choose powerful RF technologiesEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 35

Is prototyping still affordable forEuropean Academics ?Regular MPW is based onminimum area or a predefinedarea to be usedMini@sicOn Semi 0.35µ - I3T80U 80 V5M• 1,075 EUR/mm2• Minimum charge equal to10mm2• 10,750 EUROn Semi 0.35µ - I3T80U 80 V5M• 1,075 EUR/mm2• Minimum charge equal to 2mm2• 2,150 EURUMC 180nm• 13,100 EUR/block• 25mm2• 50 samplesUMC 180nm• Min charge equals 2.33mm2• 1,800 EUR/block• 35 samples1,800Europractice Service – Info Meeting – DATE2010 - 8 March 2010 - 36

Miniasic principles (1) Reducing the minimum area to be purchased (On Semi)Minimum area 10 mm2Area fitting your designEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 37

Mini@sic Example, 90nm Reducing cost by reducing the minimum block size (UMC, TSMC) )Europractice Service – Info Meeting – DATE2010 - 8 March 2010 - 38

Europractice Mini@sic TSMC offeringOverview65nmTECHNOLOGY NODE65nm MS/RF LP 1.2V/2.5V90nmTECHNOLOGY NODE90nm Logic GP 1.0V/1.8V90nm Logic GP 1.0V/2.5V90nm Logic GP 1.0V/3.3V90nm Logic GP 1.0V/1.8/3.3V90nm Logic LP 1.2V/2.5V90nm Logic LP 1.2V/3.3V90nm MS/RF GP 1.0V/2.5V90nm MS/RF GP 1.0V/3.3V90nm MS/RF GP 1.0V/1.8V/3.3V90nm MS/RF LP 1.2V/2.5V90nm MS/RF LP 1.2V/3.3V0.13µmTECHNOLOGY NODE0.13µm Logic GP 1.2V/2.5V0.13µm Logic GP 1.2V/3.3V0.13µm MS/RF GP 1.2V/2.5V0.13µm MS/RF GP 1.2V/3.3V0.18µmTECHNOLOGY NODE0.18µm Logic GP 1.8V/3.3V0.18µm MS/RF GP 1.8V/3.3V0.25µmTECHNOLOGY NODE0.25µm Logic GP 2.5V/3.3V0.25µm Logic GP 2.5V/5V0.25µm MS/RF GP 2.5V/3.3V0.25µm MS/RF GP 2.5V/5VEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 39

Europractice Mini@sic UMC offeringOverview90nm TECHNOLOGY NODE (Logic and MM/RF)1.8V or 2.5V or 3.3V I/O90nm SP_RVt 1.0V (1.2V)90nm SP_LVt 1.0V (1.2V) (RF model available)90nm SP_HVt 1.0V (1.2V)90nm LL_RVt 1.2V90nm LL_LVt 1.2V (RF model available)90nm LL_HVt 1.2V0.13µm TECHNOLOGY NODE (Logic and MMRF)3.3V I/O0.13µm HS 1.2V0.13µm SP 1.2V0.13µm LL 1.2V0.13µm HS+LL 1.2V0.13µm HS+SP 1.2V0.13µm SP+LL 1.2V0.18µm TECHNOLOGY NODE3.3V I/O0.18µm Logic G2 1.8V0.18µm Logic Low Leakage 1.8V0.18µm Mixed-Mode/RF Mode/RF 1.8VRVt : Regular Threshold Voltage deviceLVt : Low Threshold Voltage deviceHVt : High Threshold Voltage deviceEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 40

Europractice Mini@sic OnSemiOverviewOn SemiconductorAMIS 0.7µ C07M-D 2M/1P & AMIS 0.7µ C07M-A 2M/1P/PdiffC/HRAMIS 0.5µ C05M-D 3M/1P & AMIS 0.5µ C05M-A 3M/2P/HRAMIS 0.35µ C035M-D 5M/1P & AMIS 0.35µ C035M-A 5M/2P/HRAMIS 0.35µ C035U 4M (3M & 5M optional)AMIS 0.7µ C07M-I2T100 100 V - 2M & 3M optionsAMIS 0.7μ C07M-I2T30 & I2T30E 30 V - 2MAMIS 0.35µ C035 - I3T80U 80 V 4M - 3M optional (5M on special request)AMIS 0.35µ C035 - I3T50 50 V 4M - 3M optional (5M on special request)AMIS 0.35µ C035 - I3T25 3.3/25 V 4M (3M & 5M optional)Europractice Service – Info Meeting – DATE2010 - 8 March 2010 - 41

Mini@sic frequency and deadlinesEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 42

Outline TSMC technology offering and access UMC technology offering and access On Semi technology offering and access Mini@sic MEMS ConclusionEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 43

MEMSOI processTRONICS MEMS offering The MEMSOI MPW service provides access to Tronics 60µm thickSOI High Aspect Ratio Micromachining (SOI-H.A.R.M.). The technology was developed to manufacture high performancecustom inertial sensors (accelerometers and gyros).Europractice Service – Info Meeting – DATE2010 - 8 March 2010 - 44

MEMSCAP MEMS offeringEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 45

Outline TSMC technology offering and access UMC technology offering and access On Semi technology offering and access Mini@sic MEMS ConclusionEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 46

Conclusion MPW and Mini@sic offering has been expanded with TSMCTechnologies 65nm MPW and Miniasic is now available In 2009 more than 500 designs were prototyped In 2009 over 300 designs went through the Miniasic runs Advanced technology is “common” within our universities MEMS offering from MEMSCAP and TRONICS Europractice is more than ever playing a critical ii role in theeducation of microelectronics engineers in EuropeEuropractice Service – Info Meeting – DATE2010 - 8 March 2010 - 47