TetraMAX ATPG - Europractice

DatasheetTetraMAX ATPGAutomatic Test Pattern GenerationOverviewTetraMAX ® ATPG automatically generates high quality manufacturing test vectors. TetraMAX is the only ATPGsolution optimized for a wide range of test methodologies that’s integrated with Synopsys’ DFT MAX, the leadingtest synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX allows RTLdesigners to quickly create efficient, compact tests for even the most complex designs.Key Benefits• Increases product quality with generated test vectors for highdefect detection• Reduces testing costs through the use ofadvanced vector compaction techniques• Increases designer productivity by leveraging integration withSynopsys DFT MAX• Creates tests for complex and multi-million gate designsKey Features• Extremely high capacity and performance• Integrated graphical user interface• Integrated simulation waveform viewer• Integrated context-sensitive online help• Comprehensive scan design rule checking• Utilizes existing Verilog simulation libraries• DSMTest option supports testing for timing-related deepsubmicron defects• IddQTest option available for quiescent test validation• Integrated fault simulator for functional vectors• Distributed Processing runs across multiple processors• Yield Diagnostics with automatic defect isolationTesting Complex ASICsWith TetraMAX ATPG, designers can generate high qualitymanufacturing test vectors without compromising on highperformancedesign techniques. While such techniques mayimpede older generation ATPG tools, TetraMAX is able to obtaincoverage on the resulting complex logic.TetraMAX supports internal three-state busses including implementationswith pull-ups, pull-downs and charge storage. Similarto three-state busses, bi-directional I/O pads are also supported.To ensure ATE (automatic-test-equipment) requirements are met,TetraMAX provides a number of options to generate contentionfreevectors for three-state logic.Netlistw/scanHigh-Performance ATPGTestVectorsDFT MA XRTL TestDRCFull-Scan DFTAutoFixST ILProtocolTetraMAXIntegrated GUIFault SimulatorVerilog orTestGenLibraryTestReportsFigure 1: Integrated Test Flow Using TetraMax ATPG.

TetraMAX ATPGFigure 4: TetraMAX Provides High-Performance ATPGand Advanced Debug Capabilities through its IntegratedGraphical Interfaces.Figure 5: TetraMAX DelayTest Automates testing of CriticalPaths.physical defects that create a conduction path from the powersupply to ground and result in excessive current draw.TetraMAX generates a minimal set of high fault coverage vectorsfor IDDQ testing purposes, and constrains the test vectors toavoid excessive current during the quiescent state. The TetraMAXIddQTest option then accurately validates these vectors for lowquiescence using Synopsys VCS or other Verilog simulator,thereby ensuring the IDDQ vectors will work on the ATE.Distributed ProcessingFor very large designs, the TetraMAX TenX option enables ATPGand fault simulation to be run across multiple processors. TheTenX distributed processing architecture is highly scalable toover 10 processors, and compared to a single processor cangenerate test vectors in less than 1/10th time but with the samehigh test coverage and minimal vector counts. The TenX optionsupports networks with heterogeneous platforms and popularcompute management applications such as LSF.Yield DiagnosticsIn addition to identifying defective parts from manufacturing,TetraMAX ATPG can also isolate the location of defects ondevices that fail TetraMAX test vectors. Automatic andaccurate defect isolation is an important step to diagnose criticalyield issues, both during production ramp as well as in volumemanufacturing. TetraMAX diagnostics read the test vectors andtester failure data, which are the differences between measuredand expected responses to those test vectors, and report thefault candidate locations that most likely explain the faulty devicebehavior observed on the tester. TetraMAX diagnostics useadvanced heuristics and a high performance fault simulator forrapid and reliable results in a volume manufacturing environment.Netlist Formats, Testbenches, and Test Vectors InterfacesTetraMAX supports popular industry standards for netlist and testvector formats:Circuit netlist: Verilog, VHDL (87 and 93)Library: Verilog functional (Structural and UDPs)Testbench: Verilog (serial and parallel), VHDL-93(serial only)Test vectors: STIL, WGL, Toshiba TSTL2,Texas Instruments TDL91, Fujitsu FTDL,and Verilog VCDE (input only)For more information about Synopsys products, supportservices or training, visit us on the web at: www.synopsys.com,contact your local sales representative or call650.584.5000.Synopsys, Inc.700 East Middlefield RoadMountain View, CA 94043www.synopsys.com©2006 Synopsys, Inc. Synopsys, the Synopsys logo, DesignWare, VCS and Vera are registered trademarks and Design Compiler and OpenVera are trademarks of Synopsys, Inc.PCI Express, PCI-X, PCI and PCI-SIG are registered trademarks of PCI-SIG. All other products orservice names mentioned herein are trademarksof their respective holders and should be treated as such. Printed in the U.S.A. ©2006 Synopsys, Inc. 05/06.CE.06-14476