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Questa ADMS RF - Europractice

Questa ADMS RF - Europractice

Questa ADMS RF - Europractice

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<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong><strong>RF</strong> and Mixed-Signal SimulationAnalog/Mixed-Signal VerificationD A T A S H E E TKey Benefits• Minimizes risks of faulty <strong>RF</strong>/baseband connections withmore complete verifications ofcomplex <strong>RF</strong> SoC for wirelesscommunication applications• Enhances productivity because<strong>RF</strong> and baseband IC designerscan start working together, withthe same tools, much earlier inthe design process<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> is a unique simulation solution allowing efficient verification of suchcircuits. <strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> provides 100X or 1,000X speed-up ratios over regular timedomainsimulation.COMPLETE VERIFICATION OF <strong>RF</strong>-DSP SYSTEMSComplete simulation of <strong>RF</strong> system-on-chip (SoC) becomes a reality withthe combination of the Eldo ® <strong>RF</strong> capabilities into <strong>Questa</strong> ® <strong>ADMS</strong> . Builtupon these solid foundations, the <strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> solution allows effectivesimulation of communication systems containing tightly linked radiofrequency (<strong>RF</strong>) and baseband functions—analog and digital.<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong><strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> targets the simulation of systems integrating an <strong>RF</strong>front-end and baseband functions with complex digital signal processing(DSP) in VHDL or Verilog. Direct conversion receivers or amplifiers withhigh-speed digital automatic gain control (AGC) are among the simplestexamples. Verifying such systems mandates simulation solutions withwhich the transistor-level <strong>RF</strong> part can be simulated simultaneously withthe baseband part, in practical CPU time.Key Features• Uses industry-standard languagesonly, and no proprietary languages;facilitates reuse of unmodifiedlegacy code• Simulates complete systemsorders of magnitude faster thanprevious tool generation. Manymore operating conditions canbe verified• Preserves transistor-levelaccuracy wherever necessaryBUILT ON SOLID FOUNDATIONSAbout <strong>Questa</strong> <strong>ADMS</strong><strong>Questa</strong> <strong>ADMS</strong> is an industry-leading tool for mixed-signal simulation.Complex mixed-signal chips can be verified with all their analog-digitalwww.mentor.com


connections. It is a language-neutral environmentincluding SPICE, VHDL, Verilog as well as standardanalog behavioral languages such as VHDL-AMS and Verilog-A.About Eldo <strong>RF</strong>Eldo <strong>RF</strong> provides the necessary algorithms tohandle <strong>RF</strong> blocks efficiently in typical <strong>RF</strong> transceivers,such as low noise amplifiers, mixers, orvoltage controlled oscillators. It features highperformance<strong>RF</strong>-specific algorithms such as thesteady-state analysis and the modulated steadystateanalysis (MODSST). This provides the necessarysimulation speed-up for these critical blocksoperating at the highest frequencies, typicallyseveral gigaHertz.QUESTA <strong>ADMS</strong> <strong>RF</strong>—HOW DOES IT WORK ?<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> uses the MODSST algorithm ofEldo <strong>RF</strong> in place of the transient algorithm of <strong>Questa</strong><strong>ADMS</strong>. The circuit is described with any mix ofSPICE, Verilog-A, VHDL-AMS, Verilog, and VHDL.The MODSST algorithm is a mixed time-frequencyalgorithm that computes a time-varying spectrum.At discrete time points, the spectrum of the signals iscomputed using the steady-state analysis of Eldo <strong>RF</strong>.The spacing of time points is chosen to follow theslow-varying baseband information, rather than thefast-varying <strong>RF</strong> carriers.This results in huge speed-up ratios over regular transientsimulation. Two or three orders of magnitude areusual with the typical baseband-to-carrier frequencyratios in wireless networks applications.Single Kernel Architecture for <strong>RF</strong>-DSP Simulation<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> is a straightforward extension tothe single-kernel architecture of <strong>Questa</strong> <strong>ADMS</strong> andthus greatly simplifies the usage of its complex underlyingalgorithms.This architecture radically departs from so-calledco-simulation approaches where foreign simulators areglued together, using limited and cumbersome interfaces.It allows you to concentrate on design issues only, notsimulator issues. The usual <strong>Questa</strong> <strong>ADMS</strong> interface isleft unchanged, and the Eldo <strong>RF</strong> MODSST analysis isused in place of the usual transient analysis.Transistor-Level Accuracy<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> differs radically from “systemlevel”approaches, which rely on behavioral modelingbased on proprietary languages or even simple linearizationof the fast-varying <strong>RF</strong> signals. <strong>Questa</strong> <strong>ADMS</strong><strong>RF</strong> retains the full accuracy of circuit-level simulation,where and when you want it to.The critical <strong>RF</strong> blocks can be described in SPICE, sothat all high-order effects are still captured (popularfoundries deliver device model parameters for Eldo,based on the Bsim3, Bsim4, PSP, or HICUM standards).For increased performance, less critical <strong>RF</strong> oranalog blocks can be described in Verilog-A orVHDL-AMS, and all the DSP can be described inVerilog and/or VHDL.www.mentor.com


Digital Modulation for All Wireless StandardsTo simplify simulations in the context of wirelessstandards, <strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> supports all commondigital modulation formats, such as GMSK, QPSK,QAM, GFSK, EDGE, HPSK, OFDM, etc. Built-insources deliver signals modulated according to theseschemes, including the standard baseband filters suchas root cosine or Gaussian filters. The input signalcan be either explicit binary sequences or CCITTcompliantPRBS sequences.<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> displays IQ constellation diagramsand trajectories, Eye diagrams, CCDF, modulationspectrum etc. Measurement functions allow estimatingcritical figures of merit such as, ACPR, EVM, or BER.MAXIMIZE REUSE FOR MORE PRODUCTIVITY<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> uses industry-standard languagesonly: SPICE, VHDL, Verilog, Verilog-A and VHDL-AMS. Reuse of legacy code is thus greatly simplified.An existing <strong>Questa</strong> <strong>ADMS</strong> design can be importedin a matter of seconds, without any modifications,and simulated along the transistor-level mixers andVCOs of the <strong>RF</strong> front-end, whatever the feedback andcontrol loops.<strong>Questa</strong> <strong>ADMS</strong> <strong>RF</strong> is integrated in the Mentor IC Flowand also in the Cadence ® ADE framework.Mentor Graphics Analog/Mixed-Signal IC Design FlowVisit our website at www.mentor.comCopyright © 2012 Mentor Graphics Corporation. Mentor products and processes are registered trademarks of Mentor Graphics Corporation.All other trademarks mentioned in this document are trademarks of their respective owners.Corporate HeadquartersMentor GraphicsCorporation8005 S.W. Boeckman RoadWilsonville, Oregon97070-7777Phone: 503-685-7000Fax: 503-685-1204Sales and ProductInformationPhone: 800-547-3000Silicon ValleyMentor GraphicsCorporation1001 Ridder Park DriveSan Jose, California 95131 USAPhone: 408-436-1500Fax: 408-436-1501North AmericanSupport CenterPhone: 800-547-4303EuropeMentor GraphicsDeutschland GmbHArnulfstrasse 20180634 MunichGermanyPhone: +49.89.57096.0Fax: +49.89.57096.400Pacific RimMentor Graphics TaiwanRoom 1001, 10F,International Trade BuildingNo. 333, Section 1, Keelung RoadTaipei, Taiwan, ROCPhone: 886-2-87252000Fax: 886-2-27576027JapanMentor Graphics JapanCo., Ltd.Gotenyama Garden7-35, Kita-Shinagawa 4-chomeShinagawa-Ku, Tokyo 140 -0001JapanPhone: 81-3-5488-3033Fax: 81-3-5488-30049-12-MGC 1030880-w

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