Formality Equivalence Checker - Europractice

DatasheetFormality Equivalence CheckerComprehensive, Fast, IntuitiveOverviewFormality ® 2007 is an equivalence-checking (EC) solution that uses formal, static techniquesto determine if two versions of a design are functionally equivalent. EC tools verify largedesigns quickly and completely without the use of test vectors. Formality supports all majorhardware description languages, database formats, flows, and implementation designoptimizations to provide the most comprehensive verification solution available.Superior completion, time to results, and ease of use make Formality the number onecustomer-chosen EC verification solution.Key Benefits• Exhaustive verification, without test vectors, in a fraction ofthe time consumed by traditional dynamic techniques• Proves functional correctness of register retiming, complexdatapath, phase inversion, ECO, and low power implementations— from within a single product• Extends leading performance advantage with built-indistributed verification• Reduces user setup with verified automated guidance• Expands verification productivity to every engineer withflow-based graphical interface• Maximizes the life of your current hardware investmentswith leading capacity and performance• Verifies full-custom and memory designs when includingESP technologyThe Most Comprehensive Verification SolutionAdvanced Datapath VerificationFormality’s revolutionary arithmetic proof engine provides thefastest arithmetic verification performance and completion. Whiletraditional EC solutions are limited by increasing bit widths andcomplexity, Formality’s solution is fully scalable. Optimizations,such as adder tree rebalancing, resource sharing, and operatormerging can be easily verified using Formality.Figure 1: Synopsys full-chip equivalence checking.Retimed Design VerificationRetiming shifts registers across combinational logic to transferthe associated delay from a path with negative slack to aneighboring path with available slack. Circuit retiming introduceschanges that strike at the fundamental techniques used by thetypical equivalency checking tool. Formality’s breakthroughtechnology allows you to realize the QoR benefits of full-chipregister retiming in a fully verifiable flow.ECO Verification and ImplementationFormality can help debug and implement functional ECOs byidentifying areas of logic that need to be changed to bring twodesign representations into functional correlation. Additionally,

Formality Equivalence CheckerFigure 2: Problem areas can be easy identified by visual inspection of the Failing Pattern Window. In this example, the constant value oftest_se for all failing patterns indicates that it is essential to the failure and, in this case, needs to be set as a constant 0 to disable test.Formality can be used to prove that ECOs have not had anyunintentional functional impact.Low Power VerificationFormality’s built-in capabilities verify that low-power optimizationshave not changed a design’s intended functionality. Additionally,Formality contains support for RTL-driven low power implementation.Transistor VerificationESP solutions combine with Formality to offer fast verification ofcustom circuits, embedded memories, and complex I/Os. ESPtechnology directly reads existing SPICE and behavioral RTLmodelsand does not require restrictive mapping or translation.Formality’s Ease of UseFormality can account for design optimizations automaticallythrough the use of guided setup scripts generated duringimplementation. Guided setup includes information about namechanges, register optimizations, multiplier architectures, andnumerous other transformations that may occur during designimplementation. Correct-by-construction setup improves performanceand first-pass completion by utilizing the most efficient algorithmsduring matching and verification. Formality guided setupis a standard, documented format that removes dependenciesfound in tools relying on log file parsing. In the Formality flow, allinformation is independently proven and is available for your review.Hier-IQ TechnologyAn advanced way to verify designs, patented Hier-IQ technologyprovides the performance benefits of hierarchical verification with flatverification’s out-of-the-box usability. Hier-IQ technology is a primaryreason for Formality’s market-leading capacity and performance.Error-ID TechnologyError-ID identifies the exact logic causing real functional differencesbetween two design representations. Error-ID can isolateand report several logic differences when multiple discrepanciesexist. Error-ID will also present alternative logic that can bechanged to correct a given functional difference; this flexibilityallows you to select the change that is easiest to implement.Failing Pattern Display WindowView all failing input patterns in spreadsheet-like format andselect which pattern to apply to the design. The failing patternwindow is an ideal way to quickly identify trends indicating thecause of a failing verification or improper setup.Graphical User InterfaceFormality provides a flow-based environment designed topromote out-of-the-box usability. All verification and designengineers will benefit from Synopsys’ industry knowledge byoperating within an environment specifically created to matchthe way experienced verification engineers think.Accelerated Time to ResultsDistributed VerificationFormality’s leading single processor performance advantage canbe multiplied with the addition of distributed verification. Thisinherent Formality feature verifies your design using up to fourprocessors simultaneously to reduce your verification time.User-Set Effort LevelsIn Formality, you have full control over how much time and/or effortis spent verifying your design. A quick verification pass beforeaddressing the more complex points allows you to start debuggingany differences straight away.

Formality Equivalence CheckerFigure 3: Formality’s Error-ID technology enables you to quickly find, isolate, and repair functional differences.True Incremental CapabilityTo minimize iterations, matching and verification are run incrementally.Incremental matching allows you to layer available matchingtechniques and experiment with matching rules. Incrementalverification allows analysis of current results while continuing theverification of points not yet proven.Other Time Saving FeaturesFormality’s Hierarchical Scripting provides a method to investigatesub-blocks without additional setup and is ideal for isolatingproblems and verifying fixes.Formality’s Source Browsing opens RTL and netlist source filesto highlight occurrences of a selected instance. This can help userscorrelate between the RTL and gate-level design versions.Error Region Correlation provides a quick, visual identification ofthe logic from one design that correspond to the errors isolatedby Error-ID within the other.Independent VerificationValue links between implementation and verification tools significantlyimprove performance and ease of use, yet all designs continueto be read and elaborated using independent technology.Every aspect of a guided setup flow is either implicitly or explicitlyverified, and all content is available for inspection.Input FormatsSynopsys DC, DDC, MilkywaySystemVerilog 3.1aVerilog-95, Verilog-2001VHDL-87, VHDL-93Spice (Formality-ESP)Guided Setup FormatsSynopsys V-SDCFormality Guide Files (SVF)Command Line Editing allows you to take advantage of historyand common text editor commands when working from Formality’scommand line.Accurate ResultsSimulation vs Synthesis InterpretationWhen simulation and synthesis semantics differ, design intent isunclear. Formality’s RTL parsers will by default consider theseoccurrences to be errors. This is the safest approach; synthesisinterpretation may miss real design errors. Once you havedetermined that a particular coding style is safe, Formality can bedirected to obey the synthesis semantic.For more information about Synopsys products, supportservices or training, visit us on the web at:www.synopsys.com, contact your local salesrepresentative or call 650.584.5000.

Formality Equivalence CheckerSynopsys, Inc.700 East Middlefield RoadMountain View, CA 94043www.synopsys.com©2007 Synopsys, Inc. Synopsys, the Synopsys logo, and DesignWare are registered trademarks of Synopsys. AMBA and AHB is a trademark of ARM Limited in the UK. PCI Expressis a registered trademark of the PCI-SIG. Any other products or service names mentioned herein are trademarks of their respective holders and should be treated as such. Printed in theU.S.A. Printed in the U.S.A. 08/06.PS.WO.07-15169