Formality Equivalence Checker - Europractice

Formality Equivalence CheckerFigure 2: Problem areas can be easy identified by visual inspection of the Failing Pattern Window. In this example, the constant value oftest_se for all failing patterns indicates that it is essential to the failure and, in this case, needs to be set as a constant 0 to disable test.Formality can be used to prove that ECOs have not had anyunintentional functional impact.Low Power VerificationFormality’s built-in capabilities verify that low-power optimizationshave not changed a design’s intended functionality. Additionally,Formality contains support for RTL-driven low power implementation.Transistor VerificationESP solutions combine with Formality to offer fast verification ofcustom circuits, embedded memories, and complex I/Os. ESPtechnology directly reads existing SPICE and behavioral RTLmodelsand does not require restrictive mapping or translation.Formality’s Ease of UseFormality can account for design optimizations automaticallythrough the use of guided setup scripts generated duringimplementation. Guided setup includes information about namechanges, register optimizations, multiplier architectures, andnumerous other transformations that may occur during designimplementation. Correct-by-construction setup improves performanceand first-pass completion by utilizing the most efficient algorithmsduring matching and verification. Formality guided setupis a standard, documented format that removes dependenciesfound in tools relying on log file parsing. In the Formality flow, allinformation is independently proven and is available for your review.Hier-IQ TechnologyAn advanced way to verify designs, patented Hier-IQ technologyprovides the performance benefits of hierarchical verification with flatverification’s out-of-the-box usability. Hier-IQ technology is a primaryreason for Formality’s market-leading capacity and performance.Error-ID TechnologyError-ID identifies the exact logic causing real functional differencesbetween two design representations. Error-ID can isolateand report several logic differences when multiple discrepanciesexist. Error-ID will also present alternative logic that can bechanged to correct a given functional difference; this flexibilityallows you to select the change that is easiest to implement.Failing Pattern Display WindowView all failing input patterns in spreadsheet-like format andselect which pattern to apply to the design. The failing patternwindow is an ideal way to quickly identify trends indicating thecause of a failing verification or improper setup.Graphical User InterfaceFormality provides a flow-based environment designed topromote out-of-the-box usability. All verification and designengineers will benefit from Synopsys’ industry knowledge byoperating within an environment specifically created to matchthe way experienced verification engineers think.Accelerated Time to ResultsDistributed VerificationFormality’s leading single processor performance advantage canbe multiplied with the addition of distributed verification. Thisinherent Formality feature verifies your design using up to fourprocessors simultaneously to reduce your verification time.User-Set Effort LevelsIn Formality, you have full control over how much time and/or effortis spent verifying your design. A quick verification pass beforeaddressing the more complex points allows you to start debuggingany differences straight away.