64-megabit 2.7-volt Only Dual-interface DataFlash AT45DB642

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Reset Timing (Inactive Clock Polarity Low Shown)CStRECtCSSSCK/CLKtRSTRESETSO or I/O7 - I/O0(OUTPUT)SI or I/O7 - I/O0(INPUT)HIGH IMPEDANCEHIGH IMPEDANCENote:The CS signal should be in the high state before the RESET signal is deasserted.Serial/Parallel Interface TimingCSSER/PARt SPHt SPSCommand Sequence for Read/Write Operations (Except Status Register Read)SI or I/O7 - I/O0(INPUT)CMD 8 bits 8 bits 8 bitsMSBX X X XX X X XX X X X X X X X X X X X X X X XLSBPage Address(PA12 - PA0)Byte/Buffer Address(BA10 - BA0/BFA10 - BFA0)18 AT45DB<strong>64</strong>21638F–DFLSH–09/02
AT45DB<strong>64</strong>2Write OperationsThe following block diagram and waveforms illustrate the various write sequences available.FLASH MEMORY ARRAYPAGE (1056 BYTES)BUFFER 1 TOMAIN MEMORYPAGE PROGRAMBUFFER 1 (1056 BYTES)BUFFER 1WRITEMAIN MEMORYPAGE PROGRAMTHROUGH BUFFER 2MAIN MEMORY PAGEPROGRAM THROUGHBUFFER 1I/O INTERFACEBUFFER 2 TOMAIN MEMORYPAGE PROGRAMBUFFER 2 (1056 BYTES)BUFFER 2WRITESII/O7 - I/O0Main Memory Page Program through Buffers· Completes writing into selected buffer· Starts self-timed erase/program operationCSSI or I/O7 - I/O0(INPUT)CMD PA12-5 PA4-0, BFA10-8 BFA7-0n n+1 Last ByteBuffer Write· Completes writing into selected bufferCSSI or I/O7 - I/O0(INPUT)CMD X X···X, BFA10-8 BFA7-0 n n+1 Last ByteBuffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)CSStarts self-timed erase/program operationSI or I/O7 - I/O0(INPUT)CMD PA12-5 PA4-0, XXXX···XEach transitionrepresents 8 bitsn=1stbytereadn+1 = 2nd byte read191638F–DFLSH–09/02
Page 2: However, the use of either interfac
Page 5 and 6: AT45DB642As with the Continuous Arr
Page 7: AT45DB642BUFFER TO MAIN MEMORY PAGE
Page 10 and 11: This gives the DataFlash the abilit
Page 12 and 13: Table 1. Read CommandsCommand SCK/C
Page 14 and 15: Absolute Maximum Ratings*Temperatur
Page 16 and 17: AC Characteristics - Parallel Inter
Page 20 and 21: Read OperationsThe following block
Page 23 and 24: AT45DB642Detailed Bit-level Read Ti
Page 29 and 30: AT45DB642Detailed Parallel Read Tim
Page 31 and 32: AT45DB642Detailed Parallel Read Tim
Page 33 and 34: AT45DB642Figure 1. Algorithm for Pr
Page 35 and 36: AT45DB642Ordering Informationf SCKI
Page 37: Atmel HeadquartersCorporate Headqua

64-megabit 2.7-volt Only Dual-interface DataFlash AT45DB642

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