64-megabit 2.7-volt Only Dual-interface DataFlash AT45DB642

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Detailed Parallel Timing – SPI Mode 0 (Continued)Main Memory Page Read (Opcode: D2H)CSCLK 1 2 3 4 5 60 61 62 63 64 65 66 67I/O7-I/O0(INPUT)I/O7-I/O0(OUTPUT)tSUCOMMAND OPCODECMD ADDR ADDR ADDR X X X XHIGH IMPEDANCEXtVXDATA OUTDATA DATA DATADATABuffer Read (Opcode: D4H or D6H)CSCLK 1 2 3 4 5 6 7I/O7-I/O0(INPUT)I/O7-I/O0(OUTPUT)tSUCOMMAND OPCODECMD ADDR ADDR ADDR XtVHIGH IMPEDANCEDATA OUTDATA DATA DATAMSBStatus Register Read (Opcode: D7H)CSCLK1 2 3 4I/O7-I/O0(INPUT)I/O7-I/O0(OUTPUT)tSUCMDtVHIGH IMPEDANCEDATA DATA DATASTATUSREGISTER OUTPUT30 AT45DB6421638F–DFLSH–09/02
AT45DB642Detailed Parallel Read Timing – SPI Mode 3Continuous Array Read (Opcode: E8H)CSCLK 1 2 63 64 65 66 67tSUI/O7-I/O0(INPUT)I/O7-I/O0(OUTPUT)CMD ADDR X X XHIGH IMPEDANCEtVDATA OUTDATA DATA DATA DATA DATA DATA DATA DATA DATABYTE 1055OFPAGE nBYTE 0OFPAGE n+1Burst Array Read with Synchronous Delay (Opcode: E9H)CSCLK1 2 63 64 65 66 1 2 31 32 33tSU32 CLOCKSI/O7-I/O0(INPUT)I/O7-I/O0(OUTPUT)CMD ADDR X X XHIGH IMPEDANCEtVDATADATA OUTDATADATA DATA DON'T CAREDATA DATABYTE 1055OFPAGE nBYTE 0OFPAGE n+11638F–DFLSH–09/0231
Page 2: However, the use of either interfac
Page 5 and 6: AT45DB642As with the Continuous Arr
Page 7: AT45DB642BUFFER TO MAIN MEMORY PAGE
Page 10 and 11: This gives the DataFlash the abilit
Page 12 and 13: Table 1. Read CommandsCommand SCK/C
Page 14 and 15: Absolute Maximum Ratings*Temperatur
Page 16 and 17: AC Characteristics - Parallel Inter
Page 18 and 19: Reset Timing (Inactive Clock Polari
Page 20 and 21: Read OperationsThe following block
Page 23 and 24: AT45DB642Detailed Bit-level Read Ti
Page 29: AT45DB642Detailed Parallel Read Tim
Page 33 and 34: AT45DB642Figure 1. Algorithm for Pr
Page 35 and 36: AT45DB642Ordering Informationf SCKI
Page 37: Atmel HeadquartersCorporate Headqua

64-megabit 2.7-volt Only Dual-interface DataFlash AT45DB642

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