The Circuit Designer's Companion - diagramas.diagram...

138 The Circuit Designer’s Companionto exploit the region between zero V GS and V GS(off) in order to exceed the supply voltagein one direction or the other. A more subtle mechanism also affects input impedance,which is that gate leakage current is critically dependent on drain-gate voltage and draincurrent. Gate leakage current is normally characterised as I GSS , i.e. gate current with drainshorted to source. In an operational circuit, an n-channel JFET behaves differently.N-channel JFETs experience an I G “breakpoint” above which the gate current risesrapidly with increasing drain-gate voltage. This results from a phenomenon similar toavalanche breakdown but modified by the availability of carriers in the channel due todrain current. These carriers are accelerated by the drain-gate electric field and contributea leakage current through the gate because of their ionisation on impact with the silicon.Consequently, the breakpoint value depends on I D and is between a third to a half ofdrain-gate breakdown voltage, as can be seen from Figure 4.30.Figure 4.30 Plot of gate currentversus drain-gate voltage for a typicalJFET. Figure courtesy of Siliconixincorporated.Depressed Z inThe effect of this is that the input impedance of a JFET amplifier will be lower, perhapsby several orders of magnitude, than that calculated from the I GSS figure once the I Gbreakpoint is exceeded. This places a limit on the effective common mode input voltagerange. Note that p-channel JFETs, because of their lower carrier mobility, do not exhibitthe effect to anything like the same degree.In order to overcome the problem the drain-gate bias voltage must be held below thebreakpoint. A reduction in drain current will shift the breakpoint knee higher, but theimprovement is only marginal. In simple source-follower circuits it may be possible toreduce the drain bias voltage sufficiently as in Figure 4.31(a), but if the full operating